Recessed Gate Electrode Structure for Uniform HV MOS Integration
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Solution Overview
Problem
The integration of high voltage (HV) MOS devices with low voltage (LV) MOS devices in integrated circuits is challenging due to the increased height of HV MOS devices, which complicates the manufacturing process and can lead to difficulties in achieving uniform electrical properties.
Innovation Solution
A method for forming a semiconductor device with a recessed gate electrode that has high thickness uniformity, involving the formation of a recess over a substrate, deposition of a gate dielectric layer and a multilayer film comprising a gate electrode layer and sacrificial layers, followed by planarization and etching to create a recessed gate electrode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer thickness is increased for HV MOS devices, then the breakdown voltage is improved, but the device height increases making integration with LV MOS devices difficult
Solution Approach 1:
The gate electrode is recessed into the substrate along the depth dimension, allowing the gate dielectric layer to be thicker for high voltage operation while keeping the overall device height compatible with low voltage devices. This dimensional adjustment enables both HV and LV devices to coexist on the same integrated circuit without height conflicts.
2Device complexity
If the gate electrode is recessed into the substrate, then the height compatibility with LV devices is improved, but the manufacturing process complexity increases
Solution Approach 1:
The recessed structure for the gate electrode is formed in advance before depositing the gate dielectric layer and gate electrode materials. This preliminary recess formation simplifies subsequent processing steps by providing a pre-defined geometry that guides the deposition and etching processes, rather than requiring complex post-processing to achieve the recessed configuration.
Solution Approach 2:
The gate electrode is nested within the substrate by recessing it into the substrate, creating a hierarchical structure where the gate electrode occupies a lower level. This nesting approach allows the gate dielectric layer to wrap around the gate electrode from multiple surfaces, achieving the desired electrical isolation and mechanical support while maintaining height compatibility.
3Ease of manufacture
If conventional deposition methods are used for the gate electrode, then the manufacturing simplicity is maintained, but the thickness uniformity across the gate electrode is insufficient
Solution Approach 1:
The deposition process utilizes multi-angle incidence, where the deposition source moves relative to the substrate or the substrate is rotated, allowing material to deposit from different angles. This angular variation ensures that the gate electrode thickness remains uniform across the entire surface, compensating for the recessed geometry and achieving precise thickness control without requiring complex real-time monitoring systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a recessed gate electrode with high thickness uniformity and a flat top surface, leading to uniform electrical properties and improved manufacturing efficiency for both LV and HV MOS devices.
Implementation Method 1
deposition of a gate dielectric layer and a multilayer film comprising a gate electrode layer and sacrificial layers
Implementation Method 2
followed by planarization and etching to create a recessed gate electrode structure
Data Source
AI summary
Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.