Recessed Gate High-Voltage MOS Devices for Chip Area Reduction
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Solution Overview
Problem
Conventional high-voltage metal-oxide-semiconductor (HVMOS) devices face challenges in achieving higher breakdown voltage without increasing chip area and in adjusting the electrical field distribution, leading to inefficiencies in chip space utilization and leakage currents.
Innovation Solution
The introduction of a recessed structure within the semiconductor substrate, where a gate dielectric extends into the recess and covers its bottom, allowing for a vertical channel formation without increasing the chip area, and the use of a high-voltage well region with double diffusion regions to optimize the electrical field distribution and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between high-voltage junction and gate electrode is increased to increase breakdown voltage, then breakdown voltage is improved, but chip area occupied by the device increases
Solution Approach 1:
The patent introduces a recess structure that extends vertically into the substrate, transforming the horizontal distance requirement into a vertical dimension. The gate electrode is positioned within the recess, allowing the high-voltage junction to be closer horizontally to the gate while maintaining the required electrical field distance through the vertical depth of the recess. This dimensional transformation resolves the contradiction between achieving high breakdown voltage and minimizing chip area.
Solution Approach 2:
The gate electrode and gate dielectric are nested within the recess structure, which is itself formed within the substrate. This nesting allows the gate structure to occupy vertical space rather than horizontal space, enabling closer positioning of the high-voltage junction to the gate electrode in the planar direction while maintaining adequate breakdown voltage through the vertical configuration.
2Ease of manufacture
If conventional HVMOS device structure is used, then manufacturing process is simple, but electrical field distribution cannot be adjusted and leakage currents are high
Solution Approach 1:
The recess structure creates a localized region with different electrical field characteristics. By concentrating the electrical field management in the specific location of the recess, the patent enables adjusted field distribution that reduces leakage currents at critical interfaces, particularly at the high-voltage junction and gate electrode interface, while maintaining overall manufacturing simplicity.
3Device complexity
If conventional HVMOS device structure is used, then device structure is simple, but chip space utilization is inefficient
Solution Approach 1:
By utilizing the vertical dimension through the recess structure, the patent enables closer horizontal spacing of device components. The gate electrode positioned in the recess allows for reduced pitch between adjacent HVMOS devices in the planar direction, improving chip space utilization without significantly increasing overall device structural complexity.
Data Source
AI summary
An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.