Recessed Gate Structure for Dense Memory Cell Channels
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Solution Overview
Problem
The challenge in increasing the cell density of integrated chips without diminishing the performance of memory cells is due to the limitations imposed by the length of the channel region, as reducing the channel length can lead to short channel effects that negatively impact memory cell performance.
Innovation Solution
The integration of a gate structure over a recess in the substrate, where the channel region extends both laterally and vertically, allowing for a reduced lateral distance between source/drain regions while maintaining the length of the channel region, thereby increasing cell density without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel length is reduced to increase cell density, then the cell density increases, but the memory cell performance deteriorates due to short channel effects
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess in the substrate and extending the channel region vertically along the recess sidewalls. This transforms the channel from a purely lateral structure to a three-dimensional structure that utilizes vertical space, thereby increasing cell density without reducing the effective channel length that controls performance.
Solution Approach 2:
The channel region is nested within the recess structure, with the gate structure wrapping around the channel region. The channel extends laterally between source/drain regions and vertically along the recess, creating a nested configuration that maximizes space utilization while maintaining electrical control.
2Quantity of substance
If the lateral distance between source/drain regions is reduced to increase cell density, then the cell density increases, but the channel length must be reduced which causes short channel effects
Solution Approach 1:
The channel region is extended into the vertical dimension by forming it along the sidewalls of a recess in the substrate. This allows the channel to gain length in the vertical direction while the lateral footprint remains compact, thereby increasing cell density without sacrificing channel length.
Solution Approach 2:
The recess structure creates a localized region where the channel can extend vertically with different geometric properties than the lateral regions. The channel width varies along its length, being narrower in the vertical portion along the recess sidewalls, which provides better electrostatic control and mitigates short channel effects.
Data Source
AI summary
The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.