Recessed Gate MOS Transistors for Threshold Uniformity
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Solution Overview
Problem
Integrated circuits with MOS transistors face challenges in achieving uniform threshold voltage without increasing transistor area, particularly in gate replacement processes.
Innovation Solution
The solution involves forming MOS transistors with elevated LDD regions and recessed replacement gates, where LDD regions are elevated using a selective epitaxial process and gates are recessed through substrate etching, extending channel lengths and enhancing threshold uniformity without increasing transistor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel length is increased to improve threshold uniformity, then threshold uniformity is improved, but transistor area increases
Solution Approach 1:
The patent introduces vertical dimension by elevating LDD regions above the substrate surface and recessing replacement gates below the substrate surface. This creates a three-dimensional channel structure that extends threshold uniformity improvement into the vertical dimension, achieving better threshold control without increasing lateral transistor area.
Solution Approach 2:
The patent applies selective elevation to LDD regions and selective recessing to replacement gates in specific transistor portions. This local modification approach targets only the channel region needing threshold uniformity improvement, leaving other transistor areas unchanged and avoiding overall area increase.
2Manufacturing precision
If LDD regions are elevated and gates are recessed to extend channel length, then threshold uniformity is improved, but device complexity increases
Solution Approach 1:
The patent performs selective epitaxial growth to elevate LDD regions before LDD implantation, and etches substrate material to create gate recesses before forming replacement gate dielectric layers. These preliminary actions prepare the three-dimensional channel structure in advance, simplifying subsequent processing steps.
Solution Approach 2:
The patent introduces selective epitaxial growth as an intermediary process to elevate LDD regions, and uses substrate etching as an intermediary to create gate recesses. These intermediary steps enable the complex three-dimensional structure to be formed through controlled material addition and removal rather than direct complex patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases threshold uniformity of MOS transistors by extending channel lengths along both horizontal and vertical surfaces, achieving desired threshold potentials while maintaining transistor area efficiency.
Implementation Method 1
Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant
Implementation Method 2
Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material
Data Source
AI summary
An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.