Recessed Gate Nitride Semiconductor Device With Selective High-k Insulator
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Solution Overview
Problem
Existing nitride semiconductor devices face challenges in achieving high-frequency operation due to short channel effects, gate leakage current, and parasitic capacitance, particularly when the gate length is reduced below 200 nm, leading to deteriorated gate controllability and high-frequency characteristics.
Innovation Solution
A semiconductor device with a recessed gate structure is developed, featuring a gate insulating film as a stacked film of silicon nitride and a high-dielectric-constant material like AlN, Al2O3, HfO2, or ZrO2, selectively formed under the gate electrode, which improves gate controllability and reduces parasitic capacitance without increasing gate leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced below 200 nm to improve device scaling and integration density, then productivity and device density are improved, but short channel effects increase and gate controllability deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess structure in the semiconductor layer and selectively forming a high-dielectric-constant insulating film within this recess. This vertical stacking approach allows the gate insulating film to extend downward into the recess, increasing the effective gate capacitance without increasing the lateral gate length, thus maintaining gate controllability while enabling further device scaling.
Solution Approach 2:
The patent employs a composite gate insulating film structure consisting of a first insulating film (such as silicon oxide or silicon nitride) and a second high-dielectric-constant insulating film (such as AlN, HfO2, or ZrO2). This composite structure combines the benefits of different materials: the first film provides good interface characteristics and the second film provides high dielectric constant, achieving both low leakage current and high gate capacitance in scaled devices.
2Productivity
If the gate length is reduced below 200 nm to improve device scaling, then device density is improved, but parasitic capacitance increases and high-frequency characteristics deteriorate
Solution Approach 1:
The patent applies local quality by selectively forming the high-dielectric-constant insulating film only in the recess region beneath the gate electrode, while maintaining different insulating film configurations in other regions. This localized approach increases gate capacitance where needed (under the gate) without unnecessarily increasing parasitic capacitance in other areas, preserving high-frequency characteristics while enabling device scaling.
3Reliability
If a high-dielectric-constant insulating film is formed under the gate electrode to improve gate capacitance and suppress short channel effects, then gate controllability is improved, but gate leakage current may increase
Solution Approach 1:
The patent segments the gate insulating film into multiple distinct layers: a first insulating film in contact with the semiconductor layer and a second high-dielectric-constant insulating film formed on top of it within the recess. This segmentation allows the first film to provide a low-leakage interface while the second film provides high capacitance, achieving both low leakage current and high gate controllability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses short channel effects, maintains high gate capacitance, decreases interface states, and reduces parasitic capacitance, enabling high-frequency operation while preventing degradation in reliability and high-frequency characteristics.
Implementation Method 1
a gate insulating film which is a stacked film of a first insulating film and a second insulating film having a dielectric constant higher than that of the first insulating film
Data Source
AI summary
A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.