Recessed Gate Insulation With Nitrogen Barrier for Leakage Control
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Solution Overview
Problem
Manufacturing buried channel array transistors with improved electrical characteristics is challenging due to impurities in the gate insulation layer affecting electrical characteristics and leakage currents occurring at high electric field concentrations.
Innovation Solution
A semiconductor device design incorporating a substrate with a recess, a gate insulation layer, an impurity barrier layer with higher nitrogen concentration than the gate insulation layer, and multiple gate patterns with different materials and work functions, along with capping insulation patterns, to reduce impurity diffusion and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate insulation layer is formed in a recess for a buried channel array transistor, then the transistor structure is established, but impurities in the gate insulation layer diffuse into other regions and degrade electrical characteristics
Solution Approach 1:
An impurity barrier layer is introduced as an intermediary between the gate insulation layer and the substrate. This barrier layer, containing nitrogen at a concentration of 1×10^19 to 1×10^21 atoms/cm³, prevents impurities from the gate insulation layer from diffusing into the substrate and channel region, thereby resolving the impurity diffusion problem while maintaining electrical characteristics.
Solution Approach 2:
The gate structure employs a composite material approach by combining the gate insulation layer with an impurity barrier layer containing nitrogen. This composite structure leverages the nitrogen-rich barrier layer's ability to block impurity diffusion while the gate insulation layer provides electrical isolation, solving the contradiction between structural integrity and impurity prevention.
2Reliability
If the gate structure is formed with high electric field concentrations, then the transistor functionality is achieved, but leakage currents occur at concentrated electric field portions
Solution Approach 1:
The impurity barrier layer is selectively positioned at the lower portion of the recess where electric field concentration and impurity diffusion are most severe. By applying nitrogen enrichment locally at this critical region, the structure addresses the local quality of high electric field stress and impurity risk without requiring uniform modification throughout the entire gate structure.
3Reliability
If a simple gate structure is used, then manufacturing is easier, but electrical characteristics are degraded due to impurity effects
Solution Approach 1:
The gate structure is segmented into distinct functional layers: the gate insulation layer for electrical isolation and the impurity barrier layer for preventing contamination. This segmentation allows each layer to perform its specific function optimally, with the barrier layer specifically addressing impurity issues without requiring complete redesign of the entire gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the electrical characteristics of buried channel array transistors by reducing impurity diffusion and leakage currents, leading to improved transistor performance and reliability.
Implementation Method 1
an impurity barrier layer on a surface of the gate insulation layer, the impurity barrier layer covering the surface of the gate insulation layer, the impurity barrier layer having a concentration of nitrogen greater than a concentration of nitrogen included in the gate insulation layer
Data Source
AI summary
A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.