Recessed-Gate Field-Effect Transistors for Lower Off-Capacitance
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Solution Overview
Problem
Conventional field-effect transistors exhibit high off-capacitance, which negatively impacts device performance.
Innovation Solution
A structure comprising a semiconductor substrate with a recess and a shallow trench isolation region surrounding an active device region, along with a field-effect transistor featuring a gate electrode positioned on a portion of the recessed surface, is developed to reduce off-capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional field-effect transistor structure is used, then the device can be manufactured with standard processes, but the off-capacitance is excessively high which deteriorates device performance
Solution Approach 1:
The gate electrode is repositioned from a planar configuration to a three-dimensional configuration where it extends into a recess formed in the semiconductor substrate. This dimensional change allows the gate to be positioned closer to the channel region while reducing the overlap area between the gate and source/drain regions, thereby reducing off-capacitance while maintaining control over the channel.
Solution Approach 2:
The gate electrode is nested within a recess structure that is formed in the semiconductor substrate. The recess acts as a cavity that accommodates the gate electrode, allowing it to be positioned in a different spatial relationship to the source and drain regions. This nesting arrangement reduces the parasitic capacitance while maintaining effective gate control.
2Object-generated harmful factors
If the gate electrode is repositioned inside a substrate recess, then off-capacitance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The recess structure is formed in the semiconductor substrate before the gate electrode is deposited. This preliminary formation of the recess geometry allows subsequent gate electrode deposition to follow standard thin-film deposition processes, minimizing the need for additional complex manufacturing steps while achieving the desired three-dimensional gate configuration.
Data Source
AI summary
Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.