Recessed Gate Void Prevention via Plug Layer
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Solution Overview
Problem
The challenge in forming recessed gates with a lower portion wider than the upper portion is the difficulty in preventing voids from forming and moving, which can lead to electrical characteristics deterioration and operational defects due to leakage currents and threshold voltage distribution issues in semiconductor devices.
Innovation Solution
A method involving the formation of a gate recess with an upper and lower portion on a semiconductor substrate, where a gate insulation layer is formed, followed by a first silicon layer and a silicon oxide layer, and heat treatment under a reducing atmosphere to create a recess-filling layer, along with a stop layer to prevent void movement and ensure contact with the gate insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate recess is made with a lower portion wider than the upper portion, then the channel length can be sufficiently long, but voids form in the gate recess during filling
Solution Approach 1:
A plug layer is formed at the bottom of the gate recess before filling the gate electrode material. This preliminary structure prevents void formation by providing a foundation that facilitates complete filling of the wider lower portion of the recess.
Solution Approach 2:
The plug layer acts as an intermediary structure between the substrate and the gate electrode material. It mediates the filling process by preventing direct contact between the gate electrode material and the substrate, thereby eliminating void formation in the wider lower portion.
2Ease of manufacture
If the gate recess is sufficiently filled with conductive material, then the gate electrode can be formed, but voids may move and contact the gate insulation layer causing leakage current
Solution Approach 1:
The plug layer serves as a permanent intermediary barrier between the gate electrode material and the substrate. This prevents voids from moving downward and contacting the gate insulation layer, thereby eliminating leakage current paths while maintaining ease of gate electrode formation.
Solution Approach 2:
The plug layer provides beforehand cushioning by creating a physical barrier that prevents void migration. This protective structure is in place before any void movement can occur, ensuring electrical reliability is maintained throughout subsequent processing steps.
3Manufacturing precision
If the opening of the gate recess is closed during filling, then the wider lower portion cannot be sufficiently filled, but voids are trapped inside
Solution Approach 1:
The plug layer is formed in advance at the bottom of the recess, creating a foundation that enables complete filling of the wider lower portion. This preliminary structure ensures that the opening remains open during filling while the lower portion is adequately filled without trapping voids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces and prevents operational defects by ensuring the gate electrode maintains contact with the gate insulation layer, preventing leakage currents and maintaining stable threshold voltage distribution, thereby improving the production yield and reliability of semiconductor devices.
Implementation Method 1
performing heat treatment on the semiconductor substrate under a reducing atmosphere to selectively remove an oxygen component from the silicon oxide layer and to form a recess-filling layer of silicon
Implementation Method 2
performing heat treatment on the semiconductor substrate under a reducing atmosphere to selectively remove an oxygen component from the silicon oxide layer
Data Source
AI summary
A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on an inner surface of the gate recess, forming a first silicon layer on the semiconductor substrate including the gate insulation layer to form an open void within the gate recess, forming a stop layer having a high thermal resistance on the first silicon layer to prevent a void from moving around within the gate recess, forming a second silicon layer on the first silicon layer, and patterning the second and the first silicon layers to form a gate electrode.