Recessed-Gate Vertical Transistors for Lower Resistance and Capacitance
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Solution Overview
Problem
Conventional vertical transistors in semiconductor devices face issues with high off-current, which affects charge retention and electrical properties, due to sloped sidewalls and uneven critical dimensions, leading to increased external timing resistance and parasitic capacitance.
Innovation Solution
The solution involves recessing gate electrodes within the channel region of vertical transistors, creating a larger cross-sectional area in the upper region and a smaller cross-sectional area in the lower region, which reduces external timing resistance and increases drive efficiency, while also forming air gaps to decrease parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional vertical transistors with sloped sidewalls are used, then manufacturing is simpler, but external timing resistance increases and drive efficiency decreases
Solution Approach 1:
The channel region is divided into an upper region and a lower region with different cross-sectional areas. The upper region has a larger cross-sectional area to reduce external timing resistance, while the lower region has a smaller cross-sectional area to maintain proper spacing between adjacent transistors. This segmentation allows each region to optimize for its specific function.
Solution Approach 2:
The transistor structure transitions from symmetric sloped sidewalls to an asymmetric configuration where the upper region width differs from the lower region width. The upper region is widened while the lower region maintains a narrower profile, creating an asymmetric shape that simultaneously reduces resistance and maintains spacing.
2Ease of manufacture
If conventional vertical transistors with uniform channel width are used, then manufacturing is easier, but parasitic capacitance between gate electrodes increases
Solution Approach 1:
The channel region is segmented into upper and lower portions with different widths. The lower region has a smaller cross-sectional area that increases the spacing between gate electrodes of adjacent transistors, thereby reducing parasitic capacitance between them.
3Ease of manufacture
If conventional vertical transistors with sloped sidewalls are used, then patterning is simpler, but contact formation difficulty increases due to small upper region CD
Solution Approach 1:
Instead of having the channel region narrow at the top and wide at the bottom (conventional sloped sidewalls), the invention inverts this configuration by making the upper region wider than the lower region. This inversion creates a larger target area for contact formation at the upper region, significantly easing contact fabrication.
4Ease of manufacture
If conventional vertical transistors with large lower region CD are used, then manufacturing is easier, but distance between gate electrodes decreases resulting in increased shorting
Solution Approach 1:
The channel region is divided into upper and lower regions where the lower region has a reduced cross-sectional area compared to the upper region. This segmentation allows the lower region to provide adequate spacing between adjacent transistors, preventing gate electrode shorting while maintaining manufacturing feasibility.
Data Source
AI summary
An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.