Recessed Gate Structure With U-Shaped Work Function Layer
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Solution Overview
Problem
Current semiconductor structures with recessed gates face challenges in improving reliability and electrical performance.
Innovation Solution
A semiconductor structure design featuring a U-shaped work function layer with a recess and a filling layer positioned higher than the work function layer, along with conductive and dielectric layers configured as a gate, reduces resistance and enhances electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recessed gate structure is used, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) with distinct functions. The first conductive layer forms the recessed gate structure, the second conductive layer provides planarization, and the third conductive layer serves as a capping layer. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall manufacturing process.
Solution Approach 2:
The patent introduces a vertical stacking dimension by forming multiple conductive layers at different heights and positions. The first conductive layer is positioned in the recess, the second conductive layer is formed on top for planarization, and the third conductive layer provides additional protection. This multi-dimensional approach resolves the contradiction by distributing complexity across multiple layers rather than requiring a single complex structure.
2Reliability
If multiple conductive layers are added, then electrical performance is improved, but device complexity increases
Solution Approach 1:
Each conductive layer serves multiple functions simultaneously. The first conductive layer acts as both the recessed gate structure and provides electrical connectivity. The second conductive layer provides both planarization and additional electrical pathways. The third conductive layer serves as both a capping layer for protection and an additional conductive element. This multi-functionality reduces the need for separate dedicated structures, thereby reducing overall device complexity while maintaining enhanced electrical performance.
Data Source
AI summary
Disclosed is a semiconductor structure including a substrate, a first conductive layer, a second conductive layer, a work function layer, a filling layer, and a first dielectric layer. The first conductive layer is located in the substrate. The second conductive layer is located between the first conductive layer and the substrate. The work function layer is located on the first conductive layer. A cross-sectional shape of the work function layer is U-shaped and has a recess. The filling layer is located in the recess. A top surface of the filling layer is higher than a top surface of the work function layer. The first dielectric layer is located between the second conductive layer and the substrate and between the work function layer and the substrate.