Recessed Interconnect Structure Using Conductive Ink
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Solution Overview
Problem
Current semiconductor device packaging arrangements, such as package-on-package (PoP), face challenges with increased package height and warpage due to interconnect bumps, which hinder miniaturization and density improvements.
Innovation Solution
A method involving the formation of a recessed interconnect structure within an encapsulant, followed by the application of conductive ink over the surface and sidewalls of the encapsulant, creating a conductive layer that reduces package height and enhances warpage control, thereby facilitating higher density interconnects and shorter signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect bumps are used to electrically connect upper and lower semiconductor packages in PoP arrangement, then electrical connection between packages is achieved, but package height increases and warpage occurs
Solution Approach 1:
The patent extracts the protruding bump structure from the conventional PoP interconnect and replaces it with a recessed interconnect structure. The conductive ink is deposited into recesses formed in the encapsulant surface, creating flat or lowered interconnect structures that eliminate the height increase caused by traditional bumps while maintaining electrical connectivity between stacked packages.
Solution Approach 2:
Instead of building up protruding bumps for interconnection, the patent inverts the approach by creating recesses in the encapsulant and filling them with conductive ink. This inverted geometry achieves the same electrical connection function while reducing package height and improving flatness, thereby addressing the warpage issue.
2Reliability
If interconnect bumps are used for package stacking, then electrical interconnection is enabled, but warpage of the semiconductor device occurs
Solution Approach 1:
The patent removes the protruding bump geometry that causes warpage and replaces it with recessed interconnect structures. By extracting the height-increasing element and substituting it with a flat or recessed conductive ink structure, the patent maintains electrical interconnection while eliminating the mechanical stress that leads to warpage.
Solution Approach 2:
The patent applies local quality by creating recesses only in specific areas where interconnection is needed, rather than using uniform bump structures across the entire package surface. The conductive ink is selectively deposited in these localized recesses, providing targeted electrical connection without the global warpage effects of traditional bump arrays.
3Reliability
If conventional bump structures are used, then electrical connection is achieved, but package footprint and density are limited
Solution Approach 1:
The patent transitions from a vertical bump dimension to a planar recess dimension for interconnection. By moving the conductive structure into the depth of the encapsulant rather than protruding outward, the patent enables higher density interconnect arrangements within the same package footprint, effectively utilizing the third dimension (depth) to improve areal density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces package height and warpage while enabling high-density interconnects and shorter signal paths, contributing to more efficient and compact semiconductor device designs.
Implementation Method 1
forming a conductive ink over the first surface of the encapsulant, bump, and sidewall of the opening
Data Source
AI summary
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.