Recessed Interconnect Contact Layout for Misalignment Isolation
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Solution Overview
Problem
The challenge in microelectronic device fabrication is the misalignment of interconnect features between upper and underlying layers, leading to unintended electrical shorting due to technical limitations in forming scaled interconnect features, which reduces the margin for shift without increasing the pitch of the interconnect features.
Innovation Solution
The implementation of a conformal layer with a vertical clearance between interconnect features, allowing for increased lateral margin in shifting without corresponding increases in pitch, by forming a bottom interconnect feature within a recess and depositing a conformal layer that acts as an etch stop and maintains electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect features are scaled to reduced pitch, then device density is improved, but misalignment between layers causes electrical shorting
Solution Approach 1:
The patent introduces a vertical recess structure beneath the interconnect feature, creating a vertical clearance dimension. This vertical separation (at least 1 nm) provides an additional degree of freedom for maintaining electrical isolation, allowing lateral pitch to be reduced without compromising reliability due to misalignment.
2Manufacturing precision
If lateral margin for shift is increased, then misalignment tolerance is improved, but pitch of interconnect features must increase
Solution Approach 1:
The invention moves the alignment tolerance requirement from the lateral dimension to the vertical dimension by creating a recess with clearance. This allows the lateral pitch to remain tight while providing sufficient margin for lateral shifts through the vertical separation provided by the recess structure.
3Reliability
If vertical clearance is maintained, then electrical shorting is prevented, but fabrication complexity increases
Solution Approach 1:
The recess structure is formed prior to depositing the interconnect feature, establishing the vertical clearance in advance. This preliminary action ensures that the clearance is built-in from the beginning of the fabrication sequence, rather than requiring complex post-processing steps to create or maintain the separation.
Data Source
Figure 1A~1C
Figure 1D
Figure 2A~2C
AI summary
An integrated circuit device includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess. In an example, a top surface of the first interconnect feature is at least 1 nanometer (nm), or at least 3 nm, or at least 5 nm below a top surface of the first dielectric material. The second interconnect layer includes (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material. In an example, the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature. In an example, a bottom section of the second interconnect feature is within a top section of the recess.