Recessed Vertical Interconnect Layout for Reduced Package Pitch

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Solution Overview

Problem

Current solutions for package and platform miniaturization through vertical interconnects scaling, such as reduced plated through hole drill size and improved mechanical registration, incur increased manufacturing costs and assembly yield losses, and limit package and printed circuit board routing density.

Innovation Solution

The implementation of recessed vertical interconnects with crescent-shaped recessed side walls and contact pads in package substrates, allowing for reduced pitch geometry and improved electrical performance by enhancing signal and power integrity through tighter coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If reduced plated through hole drill size is used for vertical interconnects scaling, then device miniaturization is achieved, but manufacturing costs increase due to increased frequency of mechanical drill bit replacement

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing cost
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The patent transitions from traditional through-hole vertical interconnects to recessed vertical interconnects, changing the dimensional configuration by creating recesses in the substrate surface. This allows the interconnects to be formed in a recessed geometry rather than requiring complete through-holes, enabling miniaturization while using standard drill sizes and reducing manufacturing costs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies the geometric parameters of the vertical interconnects by introducing recessed side walls with specific profiles (e.g., crescent-shaped, angled, or curved surfaces). These parameter changes in the interconnect geometry enable tighter spacing and reduced pitch while maintaining manufacturing feasibility with conventional drilling and plating processes.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If reduced drill bit diameter is used, then vertical interconnects pitch is reduced, but assembly yield losses increase due to more stringent screening of parts meeting mechanical registration specifications

Engineering Contradiction:
Improvepitch geometryVSAvoidassembly yield
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

By changing from through-hole to recessed interconnect geometry, the patent enables reduced pitch spacing without proportionally reducing drill bit size. The recessed configuration allows standard-sized drills to create appropriately spaced interconnects while maintaining mechanical registration tolerances, thereby improving assembly yield.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If traditional through-hole vertical interconnects are used, then manufacturing is straightforward, but package and printed circuit board routing density is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidrouting density
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The recessed vertical interconnect configuration enables tighter spacing and higher routing density by utilizing the recessed geometry to reduce the effective pitch between adjacent interconnects. This dimensional change allows more interconnects to be packed into the same area while maintaining manufacturability through conventional processes adapted for recessed features.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12412784B2Recessed vertical interconnects for device miniaturization
Publication Date: 2025.09.09 ALTERA CORP
  • US12412784B2 patent drawing
  • US12412784B2 patent drawing
  • US12412784B2 patent drawing

AI summary

The present disclosure relates to an electronic assembly including a package substrate with a first surface and an opposing second surface; a first interconnect disposed in the package substrate and extending between the first and the second surfaces; and a second interconnect disposed in the package substrate and extending between the first and the second surfaces; wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall.