Recessed Interconnect Layout for Sub-10 nm Via Overlay Precision
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or sub-10 nanometer range due to variability and limitations in lithographic processes, leading to issues with via overlay, critical dimensions, and line width roughness, which hinder the integration of advanced metallization technologies.
Innovation Solution
The implementation of recessed interconnects and pitch quartering techniques in integrated circuit fabrication, utilizing subtractive and additive processes with materials like tungsten and titanium nitride, along with insulating caps, to pattern and recess interconnect lines and vias, and employing spacer-based pitch division for precise patterning of metal features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used for fabrication, then current manufacturing capabilities are maintained, but scaling to 10 nanometer node or sub-10 nanometer node range is limited due to variability in critical dimensions, line width roughness, and via overlay
Solution Approach 1:
The patent applies pitch quartering techniques that divide the patterning process into multiple stages, creating mandrels and spacers in sequential steps to achieve sub-lithographic pitch dimensions. This segmentation enables precise control of critical dimensions at 10nm and sub-10nm nodes by breaking down a single complex lithography step into manageable fabrication stages including mandrel formation, spacer deposition, and selective etching
Solution Approach 2:
The patent implements preliminary actions by forming recessed interconnect structures, mandrels, and spacers before final interconnect formation. These preliminary structures serve as templates that guide subsequent material deposition and patterning steps, ensuring precise via overlay and critical dimension control before the actual interconnect fabrication occurs
2Area of moving object
If feature size is scaled down to increase device density, then capacity increases, but performance optimization becomes increasingly difficult due to manufacturing variability
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional recessed structures with vertical spacers and mandrels. This dimensional change enables precise lateral pitch control through vertical spacer thickness, decoupling the lateral critical dimensions from direct lithographic resolution limits and allowing better performance control at scaled dimensions
Solution Approach 2:
The patent changes material parameters by using specific dielectric materials for spacers and mandrels with controlled deposition thicknesses. By adjusting spacer thickness through atomic layer deposition or chemical vapor deposition parameters, precise pitch control is achieved independent of lithographic wavelength limitations, maintaining manufacturing precision as device density increases
3Adaptability or versatility
If new methodologies are introduced to extend fabrication into 10 nanometer node or sub-10 nanometer node range, then scaling capability improves, but fabrication process complexity increases
Solution Approach 1:
The complex fabrication process is segmented into standardized reusable modules: mandrel formation, spacer deposition, pattern transfer, and recess etching. Each module can be independently optimized and repeated for different pitch requirements, making the complex process more manageable and adaptable across various technology nodes
Solution Approach 2:
The pitch quartering methodology and recessed interconnect structures serve multiple functions: they define pitch dimensions, provide alignment references for subsequent via formation, and create self-aligned patterns that reduce overlay complexity. This multi-functionality reduces overall process complexity despite introducing new fabrication steps
Data Source
AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive line on a conductive structure. An insulating cap is on a top of the conductive line. An ILD layer is adjacent to the conductive line, and the conductive line has an uppermost surface below an uppermost surface of the ILD layer. A conductive via is in the ILD layer and on another conductive structure. The conductive via is laterally separated from the conductive line by the insulating cap, and the conductive via has an uppermost surface above the uppermost surface of the conductive line.