Recessed Interposer Structure for Crack-Resistant Semiconductor Packages
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Solution Overview
Problem
Cracks occur in semiconductor chips during the sawing process due to the release of internal stress caused by the thermal expansion coefficient mismatch between the mold material and the wafer, leading to potential damage.
Innovation Solution
The semiconductor package design includes a substrate with a recessed interposer surface and controlled distances between layers to manage stress release during sawing, featuring recesses in the interposer and controlled layer distances to minimize stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the wafer is processed with a mold material having different thermal expansion coefficient, then the internal stress increases during mold process, but the chip becomes more susceptible to cracking during sawing process
Solution Approach 1:
The wafer is divided into multiple semiconductor chips through the sawing process. By segmenting the wafer into smaller units, the internal stress that would affect the entire wafer is distributed and reduced in each individual chip, preventing crack propagation across the whole structure.
Solution Approach 2:
The patent applies different properties to different regions of the wafer structure. Specifically, the mold material is selected with specific thermal expansion characteristics that differ from the wafer material, creating localized stress management in the mold-wafer interface region to control overall stress distribution.
2Ease of manufacture
If the internal stress is released at once during sawing process, then the cracking phenomenon occurs, but maintaining stress would prevent proper chip separation
Solution Approach 1:
The wafer is processed and mounted on the mold material before the sawing process, establishing a stress-controlled environment in advance. This preliminary positioning allows the stress to be managed during the cutting process rather than allowing sudden release, preventing cracks while enabling separation.
Solution Approach 2:
The mold material acts as an intermediary between the wafer and the external environment during sawing. This intermediate layer controls the stress release by providing a compliant interface that accommodates thermal expansion differences, allowing chip separation without sudden stress release that would cause cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses crack formation in semiconductor chips by managing stress distribution, ensuring robustness during the sawing process.
Implementation Method 1
a degree of internal stress applied to a wafer that generally has a small thickness relatively increases due to a thermal expansion coefficient between a mold material and the wafer
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a substrate including a first wiring structure, a first surface and a second surface, an interposer on the second surface, a scribe lane region, and a chip region defined by the scribe lane region, and a third surface and a fourth surface, a first semiconductor chip on the fourth surface, and a mold layer on the fourth surface, and on at least a part of a side surface of the first semiconductor chip. The third surface is closer to the substrate than the fourth surface, the third surface includes a first sub-surface corresponding to the scribe lane region and a second sub-surface corresponding to the chip region, and a distance in the first direction from the second surface to the second sub-surface is less than a distance in the first direction from the second surface to the first sub-surface.