Recessed I/O Pad Structure for Low-Capacitance Semiconductor Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D memory devices face challenges with parasitic capacitance, increased process complexity, and cost due to the thickness of insulating layers, which affects operating speed and memory density, and requires advanced technologies for forming through holes with high aspect ratios.
Innovation Solution
A semiconductor device with an input/output pad disposed in a recess penetrating the substrate, reducing parasitic capacitance and eliminating the need for thick insulating layers, allowing for easier fabrication and lower costs, while maintaining high memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the insulating layer is increased to reduce parasitic capacitance between the I/O pad and substrate, then the parasitic capacitance is reduced, but the aspect ratio of through holes increases significantly, enlarging process difficulty
Solution Approach 1:
The invention changes the spatial arrangement by forming the I/O pad structure in a recess on the substrate surface rather than on the flat substrate surface. This dimensional change allows the insulating layer to be thinner while still providing sufficient insulation, as the I/O pad is positioned lower relative to the substrate surface, reducing the capacitance coupling area without requiring increased insulating layer thickness.
Solution Approach 2:
The invention introduces a recess structure as an intermediary element between the I/O pad and the substrate. This recess acts as a mediator that provides natural electrical isolation and reduces parasitic capacitance without requiring a thick insulating layer, thereby avoiding the high aspect ratio through hole problem.
2Object-affected harmful factors
If the thickness of the insulating layer is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but more advanced technologies are required for forming through holes with larger aspect ratios, increasing device cost
Solution Approach 1:
By forming the I/O pad in a recess rather than on the flat substrate surface, the invention reduces the required insulating layer thickness to less than 1.4 microns. This eliminates the need for advanced high aspect ratio through hole formation technologies, keeping the fabrication process within standard capabilities and avoiding increased device complexity.
3Reliability
If small deviation of through holes occurs due to process error, then open circuit or current leakage occurs, but increasing insulating layer thickness does not prevent this issue
Solution Approach 1:
The recess structure serves as an intermediary that provides a larger effective opening for through hole formation compared to conventional flat surface structures. This larger opening provides greater process tolerance, allowing small deviations without resulting in open circuits or current leakage, thereby improving manufacturing reliability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess.