Recessed Element Isolation Films for MONOS Transistor Reliability
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Solution Overview
Problem
Conventional semiconductor devices with SOI substrates face challenges in maintaining transistor reliability and channel-width dependence due to the recess formation at the end portions of STI films, which affects the MONOS transistor's retention properties and channel-width variations.
Innovation Solution
A semiconductor device design with recessed element isolation films at specific depths to manage channel-width dependence and improve transistor reliability, featuring a semiconductor substrate with distinct recess depths for memory and transistor regions, formed through precise etching and ion implantation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the STI is recessed at the end portion to improve MONOS transistor reliability, then the retention property is improved, but the channel-width dependence of transistor property changes
Solution Approach 1:
The patent applies local quality by creating different recess depths at different locations of the element isolation film. Specifically, the end portion adjacent to the active region has a first recess depth, while other portions have a second recess depth that is shallower. This localized differentiation allows the film to provide both the reliability benefits of deeper recessing near the active region and the manufacturing precision of controlled recessing elsewhere, resolving the contradiction between improving retention property and maintaining channel-width dependence.
2Manufacturing precision
If chemical etching is used to form recess at STI end portion, then the recess is formed, but similar recess is also formed at SOI layer end portion causing channel-width variation
Solution Approach 1:
The patent segments the recess formation process into distinct depth zones within the element isolation film. By defining multiple recess depths (first recess depth at the end portion, second recess depth at other portions), the solution selectively affects different regions. This segmentation allows the recess to be formed where needed (at the STI end portion adjacent to active region) while controlling where it is not formed (at the SOI layer end portion), thus resolving the contradiction between achieving proper recess formation and maintaining transistor property consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses channel-width dependence variations and enhances the reliability of MONOS transistors by controlling the recess depths of element isolation films, improving the ON current and breakdown voltage of the semiconductor device.
Implementation Method 1
This method however forms a similar recess also at the end portion of the STI situated on the side of the SOI layer. Such a recess formed at the end portion of the STI situated on the side of the SOI layer inevitably changes the channel-width dependence of the property of a transistor to be formed in the SOI layer.
Implementation Method 2
formed through precise etching and ion implantation processes
Data Source
AI summary
A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.