Recessed Isolation Structures for Better GAA Gate Control
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Solution Overview
Problem
Multi-gate transistors, such as gate-all-around (GAA) FETs, face issues like poor gate control, short-channel effects, and increased capacitance due to inadequate isolation structures, leading to high sub-threshold leakage current and inefficient scaling in semiconductor devices.
Innovation Solution
A method for forming semiconductor devices involves creating a stack of alternating SiGe and Si layers, forming isolation features with a SiGe capping layer that diffuses Ge into the isolation structures, and then removing these layers to create recessed isolation features, allowing a metal gate stack to directly engage with the semiconductor fin, enhancing gate control and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used in GAA FETs, then manufacturing is simpler, but gate control deteriorates and leakage current increases
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: a first isolation layer providing electrical isolation, and a second isolation layer with recessed portions creating isolated regions. This segmentation allows the gate electrode to extend into these regions for enhanced control while maintaining manufacturing feasibility through systematic layering.
Solution Approach 2:
The patent extends the gate electrode vertically into recessed portions of the isolation structure, transitioning from planar gate control to three-dimensional gate-all-around control. This dimensional extension allows the gate to wrap around the channel from multiple directions, significantly improving control over the sub-channel region and reducing leakage current.
2Reliability
If isolation structures are added to improve gate control, then leakage current reduces, but capacitance increases
Solution Approach 1:
The isolation structure implements local quality by creating recessed portions only in specific regions where gate control is needed, rather than uniformly increasing isolation throughout. The gate electrode extends into these localized recessed regions to provide enhanced control precisely where required, minimizing unnecessary capacitance increase while effectively reducing leakage current in the sub-channel region.
3Reliability
If the gate electrode extends further into isolation regions, then gate control improves, but manufacturing precision requirements increase
Solution Approach 1:
The recessed portions of the second isolation layer are formed in advance before the gate electrode is deposited. This preliminary action creates pre-defined regions that guide the gate electrode extension, ensuring precise positioning without requiring complex real-time alignment during gate formation. The recessed structures serve as built-in templates that simplify the subsequent gate electrode deposition process.
Solution Approach 2:
The recessed portions of the second isolation layer act as intermediary structures that mediate between the planar isolation architecture and the extended gate electrode. These intermediary regions provide a controlled transition zone that facilitates precise gate electrode positioning and extension while maintaining compatibility with standard manufacturing processes, reducing the overall precision requirements compared to direct gate extension methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves gate control in the sub-channel region, reduces leakage current, and decreases capacitance, thereby enhancing the performance and efficiency of GAA FETs by ensuring better engagement between the metal gate stack and the semiconductor fin.
Implementation Method 1
depositing a capping layer including SiGe over the semiconductor fins, where Ge in the capping layer diffuses into the isolation features to form a Ge-doped layer in the isolation features
Implementation Method 2
performing an etching process to remove the Si-based and the SiGe-based capping layers, thereby removing the Ge-doped layer to form a recess in the isolation features
Data Source
AI summary
A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.