Recessed Transistor Jumper Metallization for Compact SRAM Cells
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Solution Overview
Problem
The miniaturization of SRAM bit-cells is limited by the spacing constraints of first-level interconnect metallization, which restricts the scaling of SRAM density due to the need for precise lithographic patterning and the high cost of advanced lithography techniques.
Innovation Solution
The introduction of transistor terminal jumper metallization, which electrically shunts gate, source, and drain contacts together, allowing for a relaxed mask level and reduced pitch constraints, enabling a more compact SRAM bit-cell design by recessing the jumper metallization below the height of other transistor terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If terminal contact metallization is coupled to first-level interconnect metallization through terminal contact via metallization, then electrical connection is achieved, but spacing between adjacent features becomes a limiter of SRAM bit-cell height scaling
Solution Approach 1:
The patent introduces a vertical dimension solution by coupling terminal contact via metallization to gate contact metallization through a via that extends downward from the gate contact level. This vertical via structure allows electrical connection without requiring tight lateral spacing between terminal and gate contacts, effectively using the third dimension (depth) to resolve the spacing constraint problem.
Solution Approach 2:
The gate contact metallization serves as an intermediary element that connects both the gate electrode and the terminal contact via metallization. This intermediary structure eliminates the need for direct lateral spacing constraints between terminal and gate contacts, as they are connected through the vertical via pathway rather than requiring adjacent planar placement.
2Manufacturing precision
If advanced lithography techniques are used to achieve precise patterning for smaller dimensions, then SRAM density can be increased, but manufacturing cost increases significantly
Solution Approach 1:
The patent employs self-aligned fabrication processes where the terminal contact via is automatically positioned relative to the gate contact through the via structure itself. The via extends downward from the gate contact level, creating inherent self-alignment that eliminates the need for additional lithographic alignment steps and advanced patterning techniques, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The patent merges the terminal contact formation and gate contact formation processes into a unified structure. By coupling the terminal contact via metallization to the gate contact metallization through a shared via pathway, the design combines multiple functions into a single integrated structure that can be fabricated using standard lithography processes rather than requiring separate advanced patterning steps.
3Area of stationary object
If the height of SRAM bit-cell is reduced to increase density, then more bits per chip area are achieved, but the spacing constraints of first-level interconnect metallization prevent further scaling
Solution Approach 1:
The patent resolves the bit-cell height scaling limitation by transitioning from a planar constraint problem to a vertical solution. The terminal contact via extends in the vertical dimension from the gate contact level downward, allowing the bit-cell height to be reduced in the lateral plane without being constrained by the spacing of first-level interconnect metallization, as the via connection occurs in the depth dimension rather than requiring lateral proximity.
Data Source
AI summary
Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.