Recessed Memory Package Architecture for Low-Latency IC Stacking
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Solution Overview
Problem
As computing platforms integrate more components, issues with signal integrity and power delivery arise, necessitating high-performance architectures that address these challenges.
Innovation Solution
The integration of high bandwidth memory with a processor using a recessed wafer-level package architecture, which includes direct interconnects between the CPU/SOC and memory devices, reducing signal latency and z-height through elimination of solder balls and keep-out zones, and utilizing metal redistribution layers for improved electrical performance and data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more integrated circuit devices are integrated into a single package, then functionality and operating characteristics are improved, but signal integrity and power delivery issues arise
Solution Approach 1:
The patent transitions from traditional lateral connections to vertical stacking architecture, moving components into the third dimension. Multiple memory devices are stacked above the processor package, connected through vertical interconnects (TSVs) rather than lateral traces, thereby improving signal integrity while increasing integration density
Solution Approach 2:
The patent implements a nested structure where memory devices are physically stacked and integrated within the vertical space above the processor package. The smaller memory devices are nested in the vertical dimension, creating a compact hierarchical integration that improves functionality without compromising signal integrity
2Adaptability or versatility
If more integrated circuit devices are integrated into a single package, then functionality and operating characteristics are improved, but power delivery issues arise
Solution Approach 1:
The vertical stacking architecture redistributes power delivery paths from lateral plane to vertical dimension. Power and ground signals are delivered through vertical interconnects (TSVs) that provide shorter, lower-inductance paths, improving power delivery efficiency while supporting higher integration
3Ease of manufacture
If traditional packaging with solder balls is used, then ease of manufacture is maintained, but z-height and signal latency are increased
Solution Approach 1:
The patent eliminates the traditional solder ball interface by moving connections into the vertical dimension through TSVs. This dimensional transition reduces z-height by removing the keep-out zone and solder ball assembly, while manufacturing is maintained through standardized vertical interconnect processes
4Ease of manufacture
If traditional packaging with solder balls is used, then ease of manufacture is maintained, but signal latency is increased
Solution Approach 1:
By transitioning to vertical stacking with direct TSV interconnects, the patent shortens signal paths from lateral traces through solder balls to vertical direct connections. This dimensional change reduces signal latency while maintaining manufacturing feasibility through established vertical interconnect technologies
5Manufacturing precision
If keep-out zones are maintained between adjacent components, then manufacturing precision is ensured, but device area is increased
Solution Approach 1:
The patent eliminates keep-out zones by moving component placement into the vertical dimension. Multiple memory devices are stacked above the processor package, allowing lateral space to be fully utilized while manufacturing precision is maintained through vertical alignment and TSV registration processes
Data Source
AI summary
An apparatus is provided which comprises: a first package, a second package coupled with the first package, the second package comprising a mold layer having a recess on a first mold surface, a first plurality of devices adjacent to the recess and a metal redistribution layer (RDL) coupled to a second mold surface opposite the first mold surface, wherein the mold layer includes a first thickness, wherein the recess includes a second thickness, and wherein the second thickness is less than the first thickness, and an integrated circuit device coupled with both the second package at the recess and with the first package through a plurality of solder bumps. Other embodiments are also disclosed and claimed.