Recessed Metal Interconnect Structure for CMP Stress Relief
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Solution Overview
Problem
Increasingly dense integrated circuits (ICs) face challenges in design and fabrication due to stress on conductive patterns during planarization operations, leading to potential breakage or removal of conductive patterns, which affects device performance and switching times.
Innovation Solution
An improved semiconductor device fabrication process that reduces stress between insulating layers and conductive patterns by using specific materials and techniques, such as forming metal gate structures, cap insulating layers, sidewall spacers, and interlayer dielectric layers, along with ion implantation and chemical mechanical polishing, to enhance device performance and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planarization operations are performed on increasingly dense ICs, then device integration density is improved, but stress on conductive patterns increases causing breakage or removal
Solution Approach 1:
The patent changes the physical and chemical parameters of the conductive pattern by forming a recess into the metal layer and filling it with a different material (e.g., cobalt, tungsten, or copper). This material substitution and structural modification reduces the stress experienced by the conductive pattern during planarization, preventing breakage while maintaining high integration density.
Solution Approach 2:
The conductive pattern is segmented into two parts: an upper portion that remains at the original level and a recessed lower portion that is protected from stress. This segmentation allows the structure to withstand planarization forces while maintaining electrical connectivity, thus improving reliability without sacrificing integration density.
2Reliability
If conductive patterns are protected from stress, then reliability is improved, but device performance and switching times deteriorate
Solution Approach 1:
By changing the material parameters of the conductive pattern (using materials like cobalt, tungsten, or copper with different electrical properties) and creating a recessed structure, the patent achieves both stress protection and maintained electrical performance. The recessed structure reduces stress while the carefully selected materials ensure low resistance and fast switching times.
Solution Approach 2:
The patent creates a recessed copy or replica of the original conductive pattern structure, filling it with a material optimized for both mechanical strength and electrical conductivity. This copied structure maintains the electrical function while being protected from stress, thus improving reliability without sacrificing speed.
3Speed
If resistance is reduced in conductive patterns, then switching speed is improved, but stress concentration increases causing potential breakage
Solution Approach 1:
The patent changes both the material composition and structural geometry of the conductive pattern. By using materials with low resistance (such as copper or tungsten) and forming a recessed structure with increased cross-sectional area in critical regions, the patent simultaneously reduces resistance for faster switching while increasing mechanical strength to prevent breakage.
Solution Approach 2:
The conductive pattern is formed as a composite structure combining different materials with complementary properties. The recess is filled with a material optimized for electrical conductivity, while the surrounding structure provides mechanical support. This composite approach achieves both low resistance and high strength, resolving the contradiction between switching speed and structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in improved current transition times and faster switching speeds by minimizing damage to conductive patterns and reducing resistance, thereby addressing the challenges of stress-induced issues in IC fabrication.
Implementation Method 1
performing an etching operation using a fluoride containing gas to remove one or more layers of an oxide of cobalt that are formed at or below a surface of the upper surface of the cobalt plug and remove portions of the cobalt plug below the one or more layers of the oxide
Implementation Method 2
ion implantation and chemical mechanical polishing
Implementation Method 3
ion implantation and chemical mechanical polishing
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.