Recessed High Voltage MOS Transistor for RRAM Scaling
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Solution Overview
Problem
Conventional MOS transistors face limitations in scaling due to fixed channel length, which restricts the effective miniaturization of memory cells while maintaining electrical parameters, leading to increased surface area requirements.
Innovation Solution
A recessed high voltage metal oxide semiconductor (MOS) transistor is fabricated with a gate recessed into the semiconductor substrate, allowing for an extended channel length without increasing the transistor size, achieved by forming a gate recess and depositing an insulating dielectric layer, and integrating a resistive switching device in series.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional MOS transistors are used with fixed channel length, then electrical parameters are maintained, but transistor size cannot be effectively miniaturized leading to increased surface area requirements
Solution Approach 1:
The gate is recessed into the semiconductor substrate along the vertical dimension, extending the channel length in the depth direction rather than increasing the horizontal footprint. This allows the channel length to be extended without proportionally increasing the transistor's surface area, effectively resolving the contradiction between miniaturization and electrical parameter maintenance.
Solution Approach 2:
The gate structure is nested within the semiconductor substrate by forming a recess, allowing the channel to extend into the substrate depth. This nesting approach enables the channel length to be accommodated within the existing horizontal footprint, reducing the surface area requirement while maintaining the necessary channel length for electrical performance.
2Reliability
If channel length is extended to maintain electrical parameters, then transistor performance is preserved, but transistor footprint increases reducing memory density
Solution Approach 1:
The channel length is extended by utilizing the vertical dimension through gate recess into the substrate, rather than extending horizontally. This dimensional transition allows the memory cell footprint to remain small while achieving the necessary channel length for proper transistor operation, thereby increasing memory density without sacrificing electrical performance.
Solution Approach 2:
The recessed gate structure creates a localized region with extended channel length specifically where needed for electrical performance, while the overall transistor footprint remains compact. This localized structural modification allows differential channel lengths without proportionally increasing the total memory cell area.
Data Source
AI summary
A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.