Oxide Semiconductor Vertical Transistor Structure for High On-State Current
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high on-state current, low parasitic capacitance, miniaturization, high integration, high reliability, low power consumption, and high-speed operation, particularly in transistors with oxide semiconductor layers.
Innovation Solution
The semiconductor device incorporates an oxide semiconductor layer with a specific structure involving conductive and insulating layers, including a depressed portion in the conductive layer and overlapping openings, which reduces parasitic capacitance and enhances electrical characteristics, allowing for high on-state current and miniaturization while maintaining reliability and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional transistor structure is used, then the device can be manufactured with standard processes, but the on-state current is insufficient and parasitic capacitance is high
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure by stacking multiple conductive and insulating layers in the vertical direction. This dimensional change increases the channel length without proportionally increasing the device footprint, thereby improving on-state current while managing parasitic capacitance through optimized vertical stacking of gate electrodes and insulating layers.
Solution Approach 2:
The patent employs nested stacking where multiple functional layers (conductive layers, insulating layers, oxide semiconductor layers) are arranged in a nested vertical configuration. Each layer is positioned to overlap with layers below, creating a compact nested structure that maximizes electrical performance within a minimal horizontal footprint while controlling parasitic effects.
2Productivity
If the transistor is miniaturized to increase integration density, then higher integration is achieved, but parasitic capacitance increases and electrical characteristics deteriorate
Solution Approach 1:
By moving to a vertical transistor architecture, the patent achieves miniaturization in the horizontal plane while maintaining electrical performance through the vertical stacking of functional layers. This allows higher integration density without the parasitic capacitance penalties typically associated with scaled-down planar transistors.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the transistor. The oxide semiconductor layer provides specific electrical characteristics, while the stacked conductive and insulating layers are optimized for their local functions (gate control, insulation, contact). This localized optimization maintains electrical performance despite overall miniaturization.
3Productivity
If multiple memory cells are stacked to increase density, then integration density improves, but parasitic capacitance between layers increases
Solution Approach 1:
The patent introduces insulating layers as intermediary elements between stacked conductive layers and memory cells. These insulating layers act as mediators that electrically isolate adjacent conductive structures, thereby reducing parasitic capacitance between stacked elements while still allowing the vertical stacking needed for high integration density.
Solution Approach 2:
The patent optimizes the local electrical properties of each stacked layer by selecting appropriate insulating materials and thicknesses. The insulating layers are specifically designed with properties that minimize parasitic capacitance while maintaining electrical isolation, allowing dense stacking without the harmful capacitive coupling that would otherwise occur between adjacent conductive layers.
Data Source
AI summary
A transistor that can be miniaturized is provided. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. Over the first conductive layer including a depressed portion, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer which include a first opening portion overlapping with the depressed portion are provided in this order. The third insulating layer is in contact with at least the side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the depressed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is on an inner side of the oxide semiconductor layer in the first opening portion. The fourth conductive layer is on an inner side of the fourth insulating layer in the first opening portion. In a cross-sectional view, the oxide semiconductor layer includes a region overlapping with the second conductive layer with the third insulating layer therebetween and overlapping with the fourth conductive layer with the fourth insulating layer therebetween.