Recessed Semiconductor Package Layout for Higher Bonding Density
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Solution Overview
Problem
The challenge in semiconductor package devices is the limited bonding area and connectivity issues due to reduced device sizes and increased input/output terminals, necessitating an improved bonding structure for reliable electrical connections.
Innovation Solution
A semiconductor structure with a recessed first substrate accommodating a semiconductor die, a second substrate bonded to the first substrate, and conductive connectors extending between them, allowing for increased bonding area and flexible connector layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then device density is improved, but bonding area is reduced
Solution Approach 1:
The patent introduces a recess structure that extends vertically into the substrate, transforming the bonding interface from a two-dimensional surface to a three-dimensional volume. This allows the first semiconductor die to be embedded within the recess, increasing the effective bonding area without increasing the device footprint, thereby resolving the contradiction between device density and bonding area.
Solution Approach 2:
The first semiconductor die is nested within the recess formed in the first substrate, creating a layered configuration where the die is embedded rather than surface-mounted. This nesting approach maximizes the use of vertical space, increasing device density while preserving bonding area through the recess structure.
2Adaptability or versatility
If number of input/output terminals is increased, then device functionality is improved, but bonding area is reduced
Solution Approach 1:
By creating a recess that extends vertically into the substrate, the patent transforms the bonding interface from a planar surface to a volumetric structure. This dimensional change provides additional surface area within the recess walls and bottom, enabling increased number of bonding bumps or connectors without increasing the device footprint, thus supporting enhanced device functionality.
3Reliability
If bonding area is increased to improve connectivity, then electrical connectability is improved, but device footprint is increased
Solution Approach 1:
The recess structure exploits the vertical dimension to increase bonding area. By etching a cavity into the substrate and embedding the semiconductor die within it, the design provides extended bonding surfaces on the recess walls and bottom, enabling more connectors or bonding bumps without expanding the horizontal device footprint, thus maintaining compact form factor while improving electrical connectability.
Data Source
AI summary
The present disclosure provides a semiconductor package structure and a method of manufacturing a semiconductor package structure. The semiconductor package structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side, a first semiconductor die arranged in the recess bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; and a second substrate electrically bonded to the first side of the first substrate.