Recessed Semiconductor Package Layout for Expanded Bonding Area

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Solution Overview

Problem

The semiconductor industry faces challenges in creating reliable bonding structures for advanced technology nodes due to the reduced size and increased density of semiconductor package devices, which limits the available bonding area and flexibility in connector layout, affecting electrical connectability.

Innovation Solution

A semiconductor structure is proposed that includes a recessed substrate with multiple semiconductor dies bonded on both sides, and a second substrate electrically bonded to the first substrate, allowing for increased bonding area and flexible connector placement through the use of conductive pads and molding material, enhancing bonding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the device footprint is reduced to increase device density, then the device size is reduced, but the bonding area becomes limited

Engineering Contradiction:
Improvedevice sizeVSAvoidbonding area
Core Design Contradiction:
Volume of moving objectVSArea of stationary object

Solution Approach 1:

The patent introduces a third substrate bonded to the first substrate at a location different from the semiconductor die bonding location. This creates an additional dimensional space for bonding connectors, effectively expanding the bonding area without increasing the device footprint. The connectors can be bonded between the third substrate and either the first substrate or the semiconductor die, providing multiple bonding pathways in three-dimensional space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bonding function is segmented across multiple substrates. Instead of relying on a single substrate for all bonding connections, the patent divides the bonding functionality between the first substrate (for semiconductor die bonding) and the third substrate (for connector bonding). This segmentation allows each substrate to be optimized for its specific bonding purpose while maintaining overall compactness.

Inventive Principle:
Principle #1Segmentation

2Volume of moving object

If the device footprint is reduced to increase device density, then the device size is reduced, but the flexibility in connector layout is reduced

Engineering Contradiction:
Improvedevice sizeVSAvoidconnector layout flexibility
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

By adding the third substrate bonded to the first substrate at a location distinct from the semiconductor die bonding location, the patent creates additional spatial dimensions for connector placement. This allows connectors to be positioned at multiple locations including between the third substrate and first substrate, and between the third substrate and semiconductor die, significantly improving layout flexibility within a compact footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The third substrate serves multiple functions: it provides an additional bonding interface for connectors, maintains electrical connectivity between the first substrate and external components, and enables flexible connector routing. This multi-functional design allows the same structure to accommodate various connector layouts and configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If more bonding bumps or connectors are formed to maintain electrical connectability, then the electrical connectivity is improved, but the device footprint increases

Engineering Contradiction:
Improveelectrical connectabilityVSAvoiddevice footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the third substrate to provide additional bonding surfaces for connectors in the vertical dimension. Instead of spreading connectors horizontally across a larger footprint, the connectors can be stacked or arranged in multiple layers using the third substrate as an intermediate bonding plane, thereby maintaining electrical connectability while preserving compact device dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bonding structure is nested across multiple substrate layers. The third substrate is bonded to the first substrate, creating a nested configuration where connectors can be positioned at different hierarchical levels. This nesting allows multiple bonding connections to be packed into a smaller horizontal footprint by utilizing vertical space.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases the bonding area and flexibility of connector placement, improving the electrical connectivity and compliance with design specifications without compromising device performance.

Implementation Method 1

a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate

Methodology Applied
Scientific EffectBonding: Welding

Implementation Method 2

a second substrate electrically bonded to the first side of the first substrate

Methodology Applied
Scientific EffectElectrical bonding: Welding

Data Source

PatentUS20240250039A1Semiconductor package structure and method of manufacturing the same
Publication Date: 2024.07.25 NAN YA TECH
  • US20240250039A1 patent drawing
  • US20240250039A1 patent drawing
  • US20240250039A1 patent drawing

AI summary

The present disclosure provides a semiconductor package structure and a method of manufacturing a semiconductor package structure. The semiconductor package structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side, a first semiconductor die arranged in the recess bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; and a second substrate electrically bonded to the first side of the first substrate.