Stacked Package Structure With Recessed Molding and EMI Shielding
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Solution Overview
Problem
Current advanced packaging technologies face challenges in achieving electrical connections between multiple components without increasing the package size, leading to issues such as warpage and deformation due to thermal expansion differences and the need for compact, high-density designs.
Innovation Solution
A stacked package structure and manufacturing method utilizing an upper and lower redistribution layer with embedded conductive pillars, thermal interface material, and EMI shielding, which minimizes external dimensions and maintains height, while using materials with varying coefficients of thermal expansion to prevent warpage and enhance heat dissipation and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated in one package to increase internal integration density, then electrical connection between multiple components is achieved, but package size increases
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked packaging, where chips are arranged vertically across multiple layers and connected via conductive pillars. This dimensional change enables higher integration density without increasing the package footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked within a compact package volume, with lower chips positioned beneath upper chips. The molding layer encapsulates the chips in a nested configuration, maximizing space utilization and achieving high integration density within a small package area.
2Reliability
If molding layer material is used to encapsulate chips, then chip protection is achieved, but warpage occurs due to thermal expansion differences
Solution Approach 1:
The patent modifies the physical and chemical parameters of the molding layer material, including its coefficient of thermal expansion, viscosity, and curing characteristics. By optimizing these parameters, the molding layer compensates for thermal expansion differences between chips and substrate, reducing warpage while maintaining protective encapsulation.
Solution Approach 2:
The patent employs composite molding layer materials that combine different substances with complementary properties. This composite approach allows tuning of thermal expansion characteristics and mechanical properties to match the multi-chip assembly, minimizing warpage stress while providing effective chip protection.
3Reliability
If conductive pillars are used for electrical connection between layers, then electrical connectivity is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent forms conductive pillars in advance during the packaging process, before chip stacking. The pillars are pre-formed on the substrate or intermediate layers, establishing electrical connection pathways beforehand. This preliminary action simplifies subsequent chip assembly and reduces overall manufacturing complexity.
Solution Approach 2:
The conductive pillars serve as intermediary elements that facilitate electrical connection between chips and substrate, as well as between different chip layers. These mediator structures simplify the interconnection architecture by providing dedicated vertical pathways, reducing the complexity of direct chip-to-substrate bonding.
4Area of stationary object
If package area is reduced to match chip size, then compactness is achieved, but heat dissipation becomes difficult
Solution Approach 1:
The patent moves heat dissipation from a two-dimensional surface problem to a three-dimensional solution by incorporating thermal management structures throughout the package volume. Thermal vias, heat spreaders, and thermally conductive materials are distributed across multiple layers, enabling effective heat dissipation within a compact footprint.
Solution Approach 2:
The patent introduces thermal interface materials and heat spreader structures as intermediary elements between heat-generating chips and the package exterior. These mediator components facilitate heat transfer from the chips through the molding layer to external heat sinks, maintaining compact dimensions while ensuring adequate thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables miniaturized, compact multi-chip 3D packaging with robust interconnections, improved thermal management, and reduced noise, while addressing warpage issues and enhancing electrical performance and design flexibility.
Implementation Method 1
a thermal interface material, the thermal interface material is disposed on the upper molding layer and covers the non-active surface of the first chip, and the thermal interface material is disposed between the lid and the upper molding layer
Implementation Method 2
an electromagnetic interference (EMI) shielding layer. The EMI shielding layer covers the surface of the upper molding layer
Data Source
AI summary
A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.