Recessed Semiconductor Package Layout for Lower Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The side-by-side disposition of 3D integrated circuit and memory structures on a substrate in semiconductor packages increases package size, leading to warpage issues, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor package design featuring a substrate with a recessed region for the 3D integrated circuit and a separate region for the memory structure, utilizing connecting members and a molding material to reduce warpage by controlling thickness differences between the regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the 3D integrated circuit structure and memory structure are disposed side by side on the substrate, then the dissipation characteristic is improved, but the package size is increased and warpage is generated
Solution Approach 1:
The substrate is divided into a first region with a recess for the 3D integrated circuit structure and a second region without the recess for the memory structure. This segmentation allows different structural configurations in different regions, enabling the 3D integrated circuit structure to be accommodated in the recessed first region while the memory structure is placed in the second region, thereby reducing overall package size and minimizing warpage while maintaining side-by-side arrangement for improved dissipation.
Solution Approach 2:
The substrate exhibits local quality differences between the first region containing the recess and the second region without the recess. The recess in the first region provides localized structural accommodation for the 3D integrated circuit structure, allowing it to be positioned at a lower level. This local structural variation enables compact arrangement and reduces the overall package footprint while maintaining the side-by-side configuration for thermal dissipation benefits.
2Loss of time
If the 3D integrated circuit structure and memory structure are disposed side by side on the substrate, then the manufacturing time is reduced, but the package size is increased
Solution Approach 1:
The substrate is segmented into distinct first and second regions with different structural characteristics. The first region includes a recess that accommodates the 3D integrated circuit structure, while the second region provides space for the memory structure. This segmentation enables efficient side-by-side arrangement that reduces the overall package footprint compared to traditional stacked configurations, while maintaining the simplified manufacturing process and reduced turn-around time associated with side-by-side disposition.
Solution Approach 2:
The recess in the first region creates a vertical dimension variation, allowing the 3D integrated circuit structure to be positioned at a lower level within the substrate thickness. This dimensional change enables more efficient space utilization, accommodating both the 3D integrated circuit structure and memory structure in a compact side-by-side arrangement that reduces the package's horizontal footprint while maintaining manufacturing efficiency.
Data Source
AI summary
A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.