Recessed Pad Layer Interconnect for Low-Resistance Die Bonding
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues such as increased complexity and contact resistance, particularly in the fabrication process.
Innovation Solution
A semiconductor device design featuring a recessed pad layer with a filler layer and a barrier layer, where the filler layer's upper portion increases contact surface area with the barrier layer, and the geometry of protection layers ensures void-free formation, including a bonding process, through-substrate opening formation, punch etch, isotropic etch, and conformal barrier layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pad layer is scaled down to meet increasing computing demand, then device density is improved, but contact resistance increases and fabrication complexity increases
Solution Approach 1:
The invention transitions from a two-dimensional planar contact interface to a three-dimensional recessed structure. By etching a recess into the pad layer and filling it with conductive material, the contact surface area is increased vertically, thereby reducing contact resistance while maintaining the scaled-down footprint of the device.
Solution Approach 2:
The recessed conductive structure is nested within the pad layer itself. The filler material is placed inside the recessed portion of the pad layer, creating a nested configuration that increases contact area without increasing the overall device footprint, thus maintaining high device density while improving electrical contact.
2Productivity
If the pad layer is scaled down, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct steps: forming the recess in the pad layer, depositing the barrier layer, depositing the adhesion layer, and filling with conductive material. Each step is independently controllable and optimized, making the overall complex process manageable and reproducible despite the increased number of steps.
Solution Approach 2:
The recess is pre-formed in the pad layer before subsequent layer deposition. This preliminary action creates a prepared substrate that guides the subsequent fabrication steps, ensuring proper alignment and contact between layers while simplifying the overall process flow.
3Reliability
If a shallow recess is formed in the pad layer, then contact resistance is reduced, but void formation risk increases
Solution Approach 1:
The depth of the recess is carefully controlled within specific parameters (greater than one-half but less than the full thickness of the pad layer). This parameter optimization ensures sufficient contact area reduction while maintaining structural integrity and preventing void formation during filler deposition.
Solution Approach 2:
Instead of forming a complete through-hole, only a partial recess is created. This partial action provides sufficient contact area improvement while maintaining the structural support of the pad layer, preventing collapse and void formation that would occur with excessive etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces contact resistance and improves the reliability of semiconductor devices while ensuring a high yield by increasing the contact surface area and preventing void formation during fabrication.
Implementation Method 1
conformally forming a barrier layer in the through-substrate opening and the recessed space
Implementation Method 2
conformally forming an adhesion layer in the through-substrate opening, the recessed space, and on the barrier layer
Implementation Method 3
performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer
Data Source
AI summary
The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.