Vertically Recessed Conductive Pillars for Ferroelectric Memory Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory circuitry, ferroelectric capacitors face challenges where the act of reading memory states can reverse the polarization, requiring immediate rewriting of memory cells, and existing methods for forming integrated circuitry do not efficiently create vertically recessed conductive pillars for direct electrical coupling of electronic components.
Innovation Solution
The method involves forming conductive lines with vertically recessed conductive pillars by patterning and etching conductive material, allowing for direct electrical coupling of electronic components like vertical transistors and capacitors, which are essential for stable memory cell operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ferroelectric capacitors are used in memory cells, then non-volatile data storage is achieved, but the act of reading memory states can reverse the polarization requiring immediate rewriting
Solution Approach 1:
The patent transitions from planar memory cell layouts to a three-dimensional architecture where vertical conductive pillars extend through multiple insulating layers. This vertical dimension allows for direct electrical coupling between electronic components (transistors, capacitors) without requiring lateral routing, thereby reducing the number of conductive lines and access points that could cause polarization reversal during read operations.
Solution Approach 2:
The patent introduces vertically recessed conductive pillars as intermediary structures that provide direct electrical pathways between electronic components. These pillars act as mediators that eliminate the need for traditional lateral conductive routing, reducing interference and polarization reversal risks during read operations while maintaining non-volatile data storage capability.
2Ease of manufacture
If traditional planar integration methods are used, then manufacturing processes are simpler, but direct electrical coupling of vertical transistors and capacitors is not achieved
Solution Approach 1:
The patent segments the memory cell structure into distinct vertical layers: insulating layers, vertically recessed conductive pillars, and electronic components (transistors, capacitors) positioned at different elevation levels. This segmentation allows each component to be formed through specialized processes optimized for its function, while the vertical stacking achieves high integration density without requiring complex lateral routing.
Solution Approach 2:
The patent employs vertical stacking to transition from two-dimensional planar integration to three-dimensional architecture. Conductive pillars extend vertically through insulating layers, enabling direct electrical coupling between components positioned at different heights. This dimensional transition increases integration density while maintaining manufacturing feasibility through sequential layer formation.
3Device complexity
If vertically recessed conductive pillars are formed, then direct electrical coupling of electronic components is enabled, but additional patterning and etching steps are required
Solution Approach 1:
The patent merges multiple functions into the vertically recessed conductive pillars: they serve as interconnect structures, transistor gates, and capacitor electrodes simultaneously. This consolidation reduces the total number of separate patterning and etching steps required compared to traditional planar methods where each function requires distinct structural elements and formation processes.
Solution Approach 2:
The conductive pillars are designed with multi-functionality, serving as electrical interconnects between layers, as gate electrodes for vertical transistors, and as one of the electrodes for ferroelectric capacitors. This universal structure eliminates the need for separate dedicated structures for each function, reducing manufacturing steps while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable non-volatile memory cell operation by preventing polarization reversal during reading and allows for efficient integration of memory circuitry components, enhancing data storage reliability and integration efficiency.
Implementation Method 1
One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell.
Implementation Method 2
The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars
Data Source
AI summary
A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.