Recessed Power Supply Line and 3D Source Contact for Low-Parasitic ICs
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Solution Overview
Problem
The challenge in semiconductor integrated circuits is the increase in contact resistance and parasitic capacitance due to the decrease in feature size and distance between interconnect structures, which complicates the lithography and etching processes and reduces operating speed.
Innovation Solution
The introduction of structural features for source contacts that decrease parasitic capacitance between source and drain contacts, and between source contacts and power supply lines, while also reducing contact resistance, through specific design and formation methods that relax critical dimension and process window constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then functional density increases, but contact resistance and parasitic capacitance increase
Solution Approach 1:
The source contact structure implements a nested configuration where a first source contact portion is positioned within a trench and a second source contact portion extends from the trench, creating a multi-level contact path that reduces parasitic capacitance while maintaining low contact resistance through the nested structural arrangement
Solution Approach 2:
The source contact structure transitions from a planar two-dimensional contact to a three-dimensional structure by forming a trench and positioning contact portions at different vertical levels, thereby reducing parasitic capacitance through spatial separation while maintaining electrical connectivity
2Quantity of substance
If feature size is reduced to increase integration density, then functional density increases, but parasitic capacitance increases
Solution Approach 1:
The nested source contact structure with portions at different vertical levels reduces parasitic capacitance by spatially separating the contact regions, thereby reducing harmful electromagnetic coupling while maintaining high integration density through efficient use of vertical space
Solution Approach 2:
By forming the source contact as a three-dimensional structure with portions at different heights, the design reduces parasitic capacitance through vertical separation of charge regions, effectively moving the solution from a two-dimensional plane to a three-dimensional configuration
3Quantity of substance
If feature size is reduced, then integration density increases, but critical dimension and process window requirements become more constrained
Solution Approach 1:
The source contact is divided into multiple segments (first source contact portion in the trench and second source contact portion extending from the trench), allowing each segment to be formed with relaxed dimensional constraints while collectively achieving the desired electrical connection and reducing parasitic effects
Solution Approach 2:
The segmentation is realized through three-dimensional structuring with contact portions at different vertical levels, which relaxes critical dimension requirements by distributing the electrical function across multiple spatial dimensions rather than requiring precise two-dimensional alignment
4Quantity of substance
If distance between interconnect structures is reduced, then integration density increases, but operating speed decreases due to increased parasitic capacitance
Solution Approach 1:
The nested source contact structure reduces parasitic capacitance between adjacent interconnect structures by positioning contact portions at different vertical levels, thereby reducing harmful electromagnetic coupling and improving signal transmission speed while maintaining high integration density
Solution Approach 2:
By separating contact regions in the vertical dimension, the design reduces parasitic capacitance that would otherwise slow down signal propagation, thereby improving operating speed through three-dimensional spatial arrangement while maintaining compact two-dimensional footprint
Data Source
AI summary
A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.