Recessed Source/Drain Epitaxy for Larger Backside FET Contacts
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Solution Overview
Problem
As IC devices miniaturize, the available area for forming contacts and interconnects becomes smaller, leading to increased routing complexity, parasitic resistance, and capacitance, which negatively impacts manufacturing cost and performance.
Innovation Solution
A field effect transistor (FET) structure with recessed source/drain epitaxial structures that extend below the gate structures, allowing for larger backside contacts and reduced contact resistance, and a method for fabricating this structure involving specific etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IC devices are miniaturized to advance computing power, then computing power increases, but the available area for forming contacts and interconnects becomes smaller
Solution Approach 1:
The patent extends source/drain structures vertically below the gate structure into a third dimension, creating recessed regions that provide additional space for contact formation without increasing the planar footprint. This dimensional transition from 2D to 3D allows contacts to be formed in the vertical subsurface region, effectively increasing the available area for contacts and interconnects while maintaining device miniaturization.
2Volume of moving object
If the available area for contacts and interconnects becomes smaller, then device size is reduced, but routing complexity increases
Solution Approach 1:
By creating vertically recessed source/drain structures, the patent provides additional routing space in the vertical dimension. This allows interconnects to be routed through the recessed regions without increasing planar device footprint, thereby reducing routing complexity while maintaining compact device size.
3Volume of moving object
If the available area for contacts and interconnects becomes smaller, then device miniaturization is achieved, but parasitic resistance and capacitance increase
Solution Approach 1:
The vertically extended recessed source/drain structures provide larger contact areas in the vertical subsurface region. This increased contact area reduces contact resistance and parasitic effects, while the compact planar footprint maintains device miniaturization.
4Ease of manufacture
If conventional planar source/drain structures are used, then manufacturing process is simple, but contact area is limited and contact resistance is high
Solution Approach 1:
The patent uses standard semiconductor manufacturing techniques to create vertically recessed source/drain structures. The recessed regions are formed through controlled epitaxial growth or deposition processes that extend material vertically below the gate structure, providing increased contact area without requiring complex manufacturing steps.
Data Source
AI summary
A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure disposed between first and second source/drain (S/D) structures. The gate structure comprises a vertical metal gate structure and a channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first and second S/D EPI structures horizontally through the vertical metal gate structure that at least partially surrounds the plurality of channels. At least one S/D structure comprises a lower portion that extends vertically below a bottom surface of the vertical metal gate structure, the lower portion comprising sides and a bottom surface. The FET structure also comprises frontside and backside inter-layer dielectric (ILD) layers respectively disposed above and below the vertical metal gate structure and the first and second S/D EPI structures.