Filled Recessed Semiconductor Structure for CTE Mismatch Relief
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Solution Overview
Problem
Conventional semiconductor devices face issues with excess cost, inadequate integration, decreased reliability, and low performance due to stress and thermal expansion mismatch between dissimilar materials, particularly evident in Metal-Insulator-Metal (MIM) capacitor structures and heterojunction semiconductor materials like silicon carbide (SiC) on silicon substrates.
Innovation Solution
The implementation of a filled recessed structure with a pattern of recesses in a substrate, filled with a material having a different coefficient of thermal expansion (CTE) than the substrate, to reduce stress and CTE mismatch, using materials like silicon oxide for BST MIM capacitors and SiC for SiC devices, optimizing the quantity, spacing, and dimensions of the recesses to improve structural resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dissimilar materials are used in semiconductor device structures, then device functionality and integration are improved, but stress and thermal expansion mismatch cause delamination and reliability degradation
Solution Approach 1:
The patent divides the continuous substrate into discrete regions by forming an array of recesses. The recesses segment the substrate surface, creating isolated pockets that can be filled with stress-compensating material. This segmentation allows the fill material to independently compensate for thermal expansion mismatch in each recess region, preventing large-scale delamination while maintaining overall device integration.
Solution Approach 2:
The recess fill material acts as an intermediary between the substrate and the overlying dissimilar materials. By placing this intermediate layer with appropriate mechanical properties into the recesses, the patent mediates the stress and thermal expansion mismatch between dissimilar materials, reducing delamination forces while enabling the use of dissimilar material combinations for enhanced device functionality.
2Reliability
If alumina substrates are used to match CTE with BST MIM capacitors, then thermal expansion mismatch is reduced, but manufacturing cost increases
Solution Approach 1:
Instead of requiring the entire substrate to have CTE-matched properties (global quality), the patent applies stress compensation locally only in specific recess regions. The recess fill material provides localized CTE matching and stress compensation where needed, while the bulk substrate can remain as lower-cost silicon. This local quality approach reduces overall manufacturing cost while maintaining reliability.
Solution Approach 2:
The patent creates a composite substrate structure combining silicon substrate with recess fill material. This composite structure achieves effective CTE matching for BST MIM capacitors through the fill material, while the primary silicon substrate provides cost advantages. The composite approach enables both low cost and thermal expansion compatibility.
3Productivity
If SiC is stacked on silicon substrate, then heterojunction device performance is improved, but CTE mismatch causes stress and manufacturing difficulty
Solution Approach 1:
The recess fill material serves as a pre-positioned cushioning layer that compensates for CTE mismatch before the SiC stacking process. By having the stress-compensating recesses prepared in advance on the silicon substrate, the patent reduces manufacturing difficulty during subsequent SiC deposition and bonding steps, enabling heterojunction device performance while simplifying the overall manufacturing process.
4Reliability
If recesses are added to substrate to reduce stress, then delamination resistance is improved, but device structure complexity increases
Solution Approach 1:
The recess array uses a repeating periodic pattern that can be efficiently fabricated using standard photolithography and etching processes. This regular, copyable structure reduces manufacturing complexity compared to irregular stress compensation features. The repetitive nature of the recess pattern allows for automated fabrication and simplifies process control, offsetting the added structural complexity with manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces delamination and enhances the reliability and performance of semiconductor devices by compensating for CTE mismatch, allowing for the use of lower-cost silicon substrates instead of alumina and enabling the manufacture of SiC devices with improved yield and reduced defects.
Implementation Method 1
a filled recessed structure comprising recesses extending into the substrate and having a first pattern in a plan view, the recesses spaced apart so that part of the substrate is interposed between each of the recesses; and a second material different than the first material in the recesses and having a second CTE
Data Source
AI summary
A method of manufacturing an electronic device includes providing a work piece comprising a first material, a first side, a second side opposite to the first side, and a first CTE. The method includes providing recesses extending into the work piece from the first side and comprising a pattern. The method includes providing a second material comprising a second CTE within the recesses and over the first material between the recesses. The method includes providing a third material comprising a third CTE over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.