Recessed Semiconductor Devices With Plated Edge Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase processing power without increasing the surface area of semiconductor assemblies, particularly in vertically stacked dies, where conventional interconnects like pillars or bumps limit the number of dies that can be stacked due to height constraints and require tight planarization tolerances.
Innovation Solution
The solution involves creating recesses in the semiconductor devices' edges with plated structures that electrically couple the dies, using an electroless plating process to form these structures after die stack formation, which allows for minimal height addition and increased process margins, and provides improved alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pillars or bumps are used for interconnects, then electrical coupling between dies is achieved, but the height of the vertical stack increases and the number of dies that can be stacked is limited
Solution Approach 1:
The patent extracts the interconnect function from traditional three-dimensional pillars or bumps and relocates it to two-dimensional recesses formed in the die edges. This extraction allows the interconnect structures to be embedded within the die boundary rather than extending outward, thereby achieving electrical coupling between adjacent dies without increasing the vertical stack height.
Solution Approach 2:
The patent transitions the interconnect approach from a three-dimensional vertical structure (pillars or bumps extending upward) to a two-dimensional planar structure (recesses formed in the die edge). This dimensionality change enables the interconnect to function within the same vertical envelope, allowing more dies to be stacked without increasing overall height.
2Reliability
If conventional pillars or bumps are used for interconnects, then electrical coupling is achieved, but tight planarization tolerances are required
Solution Approach 1:
The patent performs preliminary action by forming the recesses in the die edges before the die stacking process. This pre-formed recess structure provides a built-in alignment feature that guides the positioning of adjacent dies, thereby reducing the stringency of planarization tolerances required during assembly compared to conventional approaches where precise planarization must be achieved after stacking.
3Productivity
If more dies are vertically stacked to increase processing power, then functional capacity increases, but the assembly height increases
Solution Approach 1:
By extracting the interconnect function from external three-dimensional structures and embedding it within two-dimensional recesses in the die edges, the patent enables denser vertical stacking without proportionally increasing assembly height, thereby increasing processing power while maintaining compact form factor.
Solution Approach 2:
The transition from three-dimensional interconnect structures to two-dimensional recess-based interconnects frees up vertical space, allowing additional dies to be stacked within the same height envelope, thus increasing functional capacity without increasing assembly height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the vertical stacking of more semiconductor dies with minimal height increase, enhancing processing power while maintaining compactness and improving manufacturing tolerances, allowing for increased functional capacity within the same footprint.
Implementation Method 1
The plated structures can be made of copper, nickel, gold, or other suitable materials, and can be formed using an electroless plating process, for example
Data Source
AI summary
Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.