Recessed SOI Gate Structure for RF Switch Isolation and Low Ron
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Solution Overview
Problem
Current transistor devices, such as CMOS transistors, face challenges in optimizing Ron, Coff, and RFVmax values while maintaining cost-effectiveness and manufacturing simplicity, particularly due to the complexity and cost associated with thinning the substrate in RF switches.
Innovation Solution
A silicon-on-insulator (SOI) substrate with a recessed gate structure is introduced, allowing for selective thinning of the substrate only under the gate footprint, eliminating the need for re-epitaxial growth and simplifying the manufacturing process, while self-alignment of the gate ensures improved performance without degrading other device features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate is thinned to decrease Coff value, then off-state isolation is improved, but manufacturing complexity and cost increase due to regrowth processes
Solution Approach 1:
The patent applies local quality by creating a recessed gate structure that thins the substrate selectively only in the region beneath the gate footprint, while leaving the rest of the substrate at its original thickness. This localized thinning approach achieves the necessary Coff optimization for improved off-state isolation without requiring complex full-substrate thinning or regrowth processes, thereby resolving the contradiction between reliability improvement and manufacturing complexity
2Reliability
If the substrate is thinned to decrease Coff value, then off-state isolation is improved, but Ron increases due to signal loss
Solution Approach 1:
The recessed gate structure implements local quality by restricting substrate thinning to only the area directly beneath the gate, where it is needed for Coff optimization. The rest of the substrate maintains its original thickness, preserving adequate signal transmission paths and minimizing Ron increase, thus resolving the contradiction between improving off-state isolation and maintaining low signal loss
3Reliability
If selective thinning is applied to improve performance, then Ron and Coff are optimized, but manufacturing complexity increases without self-alignment
Solution Approach 1:
The recessed gate structure employs self-service through self-alignment mechanisms where the gate is formed within the recess, automatically positioning itself relative to the substrate thinning region. This self-aligning feature eliminates the need for complex additional alignment processes, allowing selective thinning to achieve Ron and Coff optimization while keeping manufacturing complexity manageable
Data Source
AI summary
A transistor device comprising a silicon-on-insulator (SOI) substrate having a plurality of polysilicon gates including a plurality of recessed gates and a plurality of non-recessed gates. The plurality of recessed gates being recessed in a top silicon layer of the SOI substrate and the plurality of non-recessed gates being on the top silicon layer. The plurality of recessed gates comprising an upper cap portion on a bottom buried portion that is in a recess of the SOI substrate. Methods of manufacturing the device are provided.