Recessed SOI Gate Structure for Short-Channel DRAM Scaling
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Solution Overview
Problem
The shrinking design rule in semiconductor device fabrication leads to increased short channel effects and junction leakage currents, making it difficult to maintain threshold voltage control and refresh characteristics due to enhanced Drain Induced Barrier Lowering (DIBL) and punch-through phenomena.
Innovation Solution
A buried insulating film is formed under the gate to create a Silicon-on-Insulator (SOI) channel region, which reduces the short channel effect and junction leakage current by using Selective Epitaxial Growth (SEG) to fill under-cut spaces and form a recessed gate structure, thereby improving the electric field and channel length body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is decreased according to shrunk design rule, then the device scaling is improved, but the threshold voltage control is worsened due to increased short channel effects
Solution Approach 1:
The patent introduces a buried insulating film beneath the channel region, transitioning from a planar structure to a three-dimensional SOI structure. This adds a vertical dimension to the channel formation, creating a suspended channel that is isolated from the substrate. This dimensional change effectively reduces short channel effects and improves threshold voltage control while maintaining scaled dimensions.
Solution Approach 2:
The buried insulating film acts as an intermediary layer between the channel region and the substrate. This intermediate layer electrically isolates the channel from the substrate, preventing charge sharing and reducing the short channel effect. The insulating film mediates the electrical interaction, allowing scaled channel lengths while maintaining voltage control.
2Productivity
If the width between gates is decreased to improve scaling, then the device density is improved, but the Drain Induced Barrier Lowering effect is increased
Solution Approach 1:
By forming the channel as a suspended structure above the buried insulating film, the patent creates vertical separation between adjacent device regions. This vertical dimension provides electrical isolation that reduces DIBL effects even when horizontal spacing between gates is minimized, enabling higher device density without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the Drain Induced Barrier Lowering effect, prevents punch-through phenomena, and enhances refresh characteristics by forming a shallow junction region, improving the overall performance of the semiconductor device.
Implementation Method 1
a buried insulating film is formed under a gate to form a SOI (Silicon-on-Insulator) channel region
Implementation Method 2
using Selective Epitaxial Growth (SEG) to fill under-cut spaces and form a recessed gate structure
Data Source
AI summary
A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.