Recessed SOI Source Drain Epitaxy
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Solution Overview
Problem
High source and drain resistance in field effect transistors on extremely thin semiconductor-on-insulator (ETSOI) devices limits on-current and overall performance due to the reduction in thickness of the source and drain regions.
Innovation Solution
A semiconductor-on-insulator substrate with a buried single crystalline rare earth oxide layer is used, where recessed source and drain trenches are formed, and single crystalline semiconductor material is epitaxially aligned with the buried oxide layer to reduce parasitic capacitive coupling and increase the thickness of the source and drain regions, thereby lowering resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the top semiconductor layer thickness is reduced to create extremely thin SOI devices, then device scaling and integration density are improved, but source and drain resistance increases significantly degrading performance
Solution Approach 1:
The invention extends the source and drain regions vertically into the buried oxide layer, transitioning from a two-dimensional planar configuration to a three-dimensional structure. This vertical extension into the z-dimension allows the source and drain regions to maintain sufficient volume and cross-sectional area for low resistance while keeping the top semiconductor layer thickness reduced for scaling.
Solution Approach 2:
The source and drain regions are nested within the buried oxide layer, with the recessed portions embedded in the oxide matrix. This nesting approach allows the conductive regions to be housed within the insulating oxide layer, providing electrical isolation while maintaining low resistance through the extended vertical dimension.
2Reliability
If recessed source and drain regions are formed deeper into the buried oxide layer, then source and drain resistance is reduced, but parasitic capacitive coupling with the gate electrode increases
Solution Approach 1:
The invention applies different properties to different regions: the recessed source and drain regions have high conductivity for low resistance, while the surrounding buried oxide layer maintains its insulating properties to provide electrical isolation. The gate dielectric layer is selectively positioned to minimize capacitive coupling only in the critical regions where it would be most harmful.
Solution Approach 2:
The gate dielectric layer acts as an intermediary between the gate electrode and the recessed source and drain regions. This intermediate layer provides electrical isolation that reduces parasitic capacitive coupling while allowing the source and drain regions to extend deeply into the buried oxide layer for low resistance.
3Manufacturing precision
If epitaxial alignment with the buried oxide layer is implemented, then crystal structure compatibility and material quality are improved, but manufacturing complexity increases
Solution Approach 1:
The invention utilizes the lattice constant compatibility between silicon and certain rare earth oxides (such as gadolinium oxide and neodymium oxide) to enable epitaxial growth. By selecting specific oxide materials with matching crystal structures and adjusting growth parameters, high-quality single crystalline source and drain regions can be formed through the oxide layer with controlled orientation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes parasitic capacitive coupling while providing low source and drain resistance, enhancing the performance of ETSOI devices by increasing the thickness of the recessed source and drain regions relative to the thin top semiconductor layer.
Implementation Method 1
An embedded single crystalline semiconductor portion epitaxially aligned to the underlying buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench
Data Source
AI summary
After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.