Recessed Solder Bump IC Structure for High Current
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Solution Overview
Problem
Conventional C4 solder bumps have a limited current carrying capacity, restricting the amount of current that can be transmitted through semiconductor integrated circuit (IC) components, which is further constrained by design limitations and surface area requirements.
Innovation Solution
The development of IC structures with recessed solder bump areas and methods for forming these structures, where a semiconductor material has both recessed and non-recessed areas, with through-semiconductor vias (TSVs) protruding from the recessed areas and a metal layer electrically connected to the TSVs, allowing for larger solder bumps and increased current transmission with reduced surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional C4 solder bumps are used to connect IC dies to packaging, then the structure is simple and easy to manufacture, but the current carrying capacity is limited to approximately 0.200 A
Solution Approach 1:
The patent transitions from a conventional flat solder bump structure to a three-dimensional structure by forming a recess in the substrate and positioning the solder bump within it. This vertical dimensionality change allows the solder bump to be larger in volume while maintaining a compact footprint, thereby increasing current carrying capacity without proportionally increasing surface area.
Solution Approach 2:
The solder bump is nested within a recess formed in the substrate, creating a nested configuration where the bump is partially embedded. This nesting approach allows the connection structure to occupy less surface area while providing a larger effective connection volume for current flow, resolving the contradiction between current capacity and structural simplicity.
2Reliability
If multiple C4 solder bumps are electrically connected to a single TSV to increase current capacity, then the current carrying capacity improves, but the surface area required for electrical connection increases
Solution Approach 1:
By forming a recess in the substrate and positioning a single larger solder bump within it, the patent utilizes the vertical dimension to increase the effective connection area for current flow. This allows one bump to provide the current capacity of multiple bumps without requiring multiple surface footprints, thus increasing current capacity while reducing surface area.
Solution Approach 2:
The patent merges multiple potential bump functions into a single integrated structure by forming one recess that contains a solder bump connected to a TSV. This consolidation achieves the current carrying capacity of multiple bumps while using the surface area of only one bump location, effectively combining the electrical connection functions.
3Reliability
If larger solder bumps are formed to increase current carrying capacity, then the current transmission improves, but the surface area required for the connection increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through recess formation. The solder bump is positioned within a recess that extends below the substrate surface, allowing the bump to have a larger volume and cross-sectional area for current flow while its projection on the surface remains compact. This enables larger effective area for current carrying without proportionally increasing the surface footprint.
Data Source
AI summary
Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC structure according to embodiments of the present disclosure can include: a semiconductor material, wherein an upper surface of the semiconductor material includes a non-recessed area and a recessed area laterally separated from each other, the recessed area of the upper surface being shaped to receive a solder bump therein; at least one first through-semiconductor via (TSV) positioned within the semiconductor material and including an upper surface protruding from the recessed area of the semiconductor material; and a metal layer formed over the recessed area and electrically connected to the at least one first TSV.