Recessed Source Drain Regions Reduce Fringe Capacitance
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Solution Overview
Problem
The use of silicon nitride spacers in semiconductor device fabrication leads to increased fringe capacitance due to their high dielectric constant, which deteriorates dynamic switching speed and results in longer rise/fall times for transistors, especially in PMOS transistors with epitaxial silicon germanium regions.
Innovation Solution
A method involving the formation of recessed source/drain regions using a combination of silicon dioxide and silicon nitride sidewall spacers, with silicon dioxide positioned between the gate electrode and conductive contacts to reduce fringe capacitance, and epitaxial deposition of silicon-germanium regions followed by common etching to define recessed regions, thereby minimizing silicon-germanium material above the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon nitride spacers are used in semiconductor device fabrication, then the manufacturing process is simplified and spacers can be readily etched, but fringe capacitance increases due to high dielectric constant, deteriorating dynamic switching speed
Solution Approach 1:
The patent divides the spacer structure into two distinct segments: a first spacer made of silicon dioxide and a second spacer made of silicon nitride. This segmentation allows each material to fulfill its specific function - the silicon dioxide first spacer reduces fringe capacitance while the silicon nitride second spacer provides ease of removal during fabrication.
Solution Approach 2:
The patent applies different materials with different properties to different locations in the spacer structure. The first spacer (silicon dioxide) is positioned where fringe capacitance reduction is critical (closer to the gate electrode), while the second spacer (silicon nitride) is positioned where ease of removal is prioritized. This local differentiation optimizes both electrical performance and manufacturability.
2Ease of manufacture
If silicon nitride spacers are used, then spacer formation is easier, but rise/fall times increase due to increased fringe capacitance
Solution Approach 1:
The patent divides the spacer structure into two distinct segments: a first spacer made of silicon dioxide and a second spacer made of silicon nitride. This segmentation allows each material to fulfill its specific function - the silicon dioxide first spacer reduces fringe capacitance while the silicon nitride second spacer provides ease of removal during fabrication.
Solution Approach 2:
The patent applies different materials with different properties to different locations in the spacer structure. The first spacer (silicon dioxide) is positioned where fringe capacitance reduction is critical (closer to the gate electrode), while the second spacer (silicon nitride) is positioned where ease of removal is prioritized. This local differentiation optimizes both electrical performance and manufacturability.
3Reliability
If epitaxial silicon germanium regions are formed in PMOS transistors, then device performance is enhanced, but fringe capacitance increases due to material properties
Solution Approach 1:
The patent extracts or removes the problematic high-dielectric constant material (silicon nitride) from the critical region near the gate electrode where it would increase fringe capacitance. Instead, a low-dielectric constant material (silicon dioxide) is used in that specific location, while the epitaxial silicon germanium regions are retained in the source/drain areas where they provide performance benefits without directly contributing to fringe capacitance issues.
Solution Approach 2:
The patent applies different materials with different properties to different locations in the spacer structure. The first spacer (silicon dioxide) is positioned where fringe capacitance reduction is critical (closer to the gate electrode), while the second spacer (silicon nitride) is positioned where ease of removal is prioritized. This local differentiation optimizes both electrical performance and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fringe capacitance and enhances the dynamic switching speed of transistors by optimizing the placement and material choice of spacers, improving the performance of both NMOS and PMOS transistors.
Implementation Method 1
silicon dioxide positioned between the gate electrode and conductive contacts to reduce fringe capacitance
Implementation Method 2
performing an epitaxial deposition process to form raised silicon-germanium regions in the cavities
Implementation Method 3
performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor
Data Source
AI summary
In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.