Recessed Source/Drain Contacts for Gate Placement
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Solution Overview
Problem
In modern integrated circuits, the positioning of gate contacts above isolation regions to avoid electrical shorts results in reduced packing density and increased capacitance due to the need for minimum spacing between gate and source/drain contacts.
Innovation Solution
The method involves forming recessed source/drain contact structures above the active region, allowing for the placement of gate contacts directly above the active region while maintaining dielectric separation, thereby reducing capacitance and increasing packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contacts are positioned above isolation regions to avoid electrical shorts, then reliability is improved, but packing density deteriorates
Solution Approach 1:
The patent applies dimensionality change by recessing the source/drain contacts vertically into the interlayer dielectric layer, creating a stepped configuration. This vertical positioning adjustment allows gate contacts to be placed above the active region while maintaining adequate separation from source/drain contacts, thus improving packing density without compromising reliability against electrical shorts.
2Reliability
If gate contacts are positioned above isolation regions to avoid electrical shorts, then reliability is improved, but capacitance increases
Solution Approach 1:
By recessing source/drain contacts vertically into the interlayer dielectric layer, the patent reduces the overlapping area between gate contacts and source/drain contacts. This dimensional adjustment decreases parasitic capacitance while maintaining reliable electrical isolation, thus resolving the contradiction between reliability improvement and capacitance reduction.
Solution Approach 2:
The patent extracts the source/drain contacts from their conventional position above the active region and relocates them vertically into the interlayer dielectric layer. This extraction removes the source of excessive capacitance generation while preserving the electrical short prevention function, thereby reducing harmful capacitive effects.
3Reliability
If minimum spacing is maintained between gate and source/drain contacts, then reliability is improved, but packing density deteriorates
Solution Approach 1:
The patent utilizes vertical dimensionality by recessing source/drain contacts into the interlayer dielectric layer, creating a stepped structure. This allows gate contacts to be positioned closer horizontally while maintaining adequate vertical separation, thus improving packing density without sacrificing reliability through the creation of three-dimensional spatial separation.
Data Source
AI summary
A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a plurality of gate structures, a spacer formed adjacent each of the plurality of gate structures, and conductive source/drain contact structures positioned adjacent each of the plurality of gate structures and separated from the associated gate structure by the spacer. A first portion of the conductive source/drain contact structures of a subset of the plurality of gate structures is recessed at a first axial position along a selected gate structure of the plurality of gate structures to define a cavity. A selected source/drain contact structure is not recessed. A first dielectric layer is formed in the cavity. A conductive line contacting the selected source/drain contact structure in the first axial position is formed.