Recessed Gate Spacer Profiles for Void-Free Inter-Gate Dielectric Fill
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Solution Overview
Problem
The semiconductor industry faces challenges in filling dielectric material between adjacent gate structures on integrated chips due to the high aspect ratio trenches created by reduced minimum feature sizes, leading to void formation and increased time-dependent dielectric breakdown (TDDB) and device failure.
Innovation Solution
The method involves forming sidewall spacers that are recessed below the uppermost surfaces of gate structures to facilitate better dielectric fill between adjacent gate structures, using a two-step etching process to create a first plurality of sidewall spacers recessed below the uppermost surfaces of the first gate structures and a second plurality of sidewall spacers with a smaller height, allowing for improved dielectric material deposition without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase the number of transistors on an integrated chip, then the transistor density is improved, but the aspect ratio of trenches between adjacent gate structures increases, leading to void formation in dielectric material
Solution Approach 1:
The patent segments the gate structures into different height levels by forming first and second gate structures with different heights. This segmentation allows the trenches between adjacent gate structures to have varying aspect ratios, with lower gate structures creating shallower trenches that are easier to fill with dielectric material without void formation.
Solution Approach 2:
The patent applies local quality by creating different structural configurations in different regions of the integrated chip. Specifically, first gate structures have higher heights while second gate structures have lower heights, allowing each region to be optimized for its specific electrical and mechanical requirements while managing the overall dielectric fill quality.
2Reliability
If the gate structure height is increased to improve transistor performance, then the electrical performance is improved, but the aspect ratio of adjacent trenches increases, causing void formation and TDDB
Solution Approach 1:
The patent segments the gate structures into different height categories, with first gate structures having higher heights for optimal electrical performance and second gate structures having lower heights to create shallower trenches. This segmentation allows high-performance transistors to coexist with regions optimized for reliable dielectric filling.
Solution Approach 2:
The patent introduces an intermediate structural solution by forming second gate structures with lower heights that act as mediators between the high-performance first gate structures and the dielectric material. These intermediate structures reduce the aspect ratio of adjacent trenches, preventing void formation and TDDB while maintaining overall device performance.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.