Recessed Storage Node Capacitor for DRAM Integration
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in achieving sufficient cell capacitance due to limited planar area, making it difficult to obtain reliable operation, particularly in DRAM devices, as existing technologies struggle to increase capacitance effectively.
Innovation Solution
The method involves forming a storage node in semiconductor devices by creating a recessed conductive pattern within a contact hole, using titanium nitride layers and sacrificial layers, with specific etching and deposition processes to optimize the structure and increase capacitance, including the use of ammonium hydroxide as a wet etchant and sulfuric acid for cleaning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the planar area of unit cell is reduced to achieve higher integration, then device density increases, but cell capacitance becomes insufficient for reliable operation
Solution Approach 1:
The patent transitions from planar storage nodes to three-dimensional cylindrical storage nodes. The contact holes are formed with depths of at least 18000 Å, creating vertical capacitance accumulation that compensates for reduced planar area. This dimensional change allows sufficient capacitance to be achieved within highly integrated unit cells.
2Reliability
If the thickness of dielectric layer is reduced to increase capacitance in limited area, then capacitance density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
Instead of reducing dielectric layer thickness, the patent increases capacitance by extending the storage node depth to at least 18000 Å. This vertical extension provides additional capacitance accumulation surface area without requiring ultra-thin dielectric layers, thereby avoiding stringent thickness control requirements.
3Reliability
If deep contact holes are formed to create three dimensional storage nodes, then capacitance increases, but etching process complexity and difficulty increase
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary structure during the formation of deep contact holes. This sacrificial layer enables controlled etching to the required depth of at least 18000 Å while providing a reference for subsequent storage node formation, thereby managing the complexity of the deep etching process.
4Reliability
If recessed conductive patterns are formed to increase overlap area, then capacitance increases, but manufacturing steps and process complexity increase
Solution Approach 1:
The patent forms the recessed conductive pattern structure during the initial contact hole formation process, before subsequent storage node fabrication steps. By preliminarily establishing the deep contact hole structure with sufficient overlap area, the patent achieves the required capacitance without adding separate recess formation steps, thereby reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of storage nodes with increased capacitance by optimizing the structure and dimensions of the conductive patterns, enhancing the overlap area between the storage node and the plate node, thereby improving the capacitance of capacitors in a limited planar area.
Implementation Method 1
The second sacrificial layer pattern may be removed using a wet etching process that employs an ammonium hydroxide (NH4OH) solution as a wet etchant
Implementation Method 2
The first storage node conductive pattern may be recessed using a cleaning process that employs a sulfuric acid (H2SO4) solution as a cleaning solution
Implementation Method 3
The titanium nitride (TiN) layer may be formed to a thickness of about 50 angstroms (Å) to about 150 angstroms (Å) using, for example, an atomic layer deposition (ALD) process
Implementation Method 4
The titanium nitride (TiN) layer may be formed to a thickness of about 50 angstroms (Å) to about 150 angstroms (Å) using, for example, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process
Data Source
AI summary
Methods of forming a storage node in a semiconductor device are provided. The method includes forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node.