Recessed Thin-Channel TFT Structure for Better Gate Control
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Solution Overview
Problem
Thin-film transistors (TFTs) face performance issues due to thick bodies leading to poor electrostatic gate control, subthreshold swing degradation, and challenges in damascene contact etch processes, particularly with thin channel materials being prone to removal during chemical mechanical planarization.
Innovation Solution
A recessed thin-channel TFT is formed by recessing the back-channel of the TFT, reducing its thickness relative to the source and drain regions, allowing for self-aligned processing and improved electrostatics and short-channel control, which enhances gate control and reduces the need for aggressive contact etches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel region is made thinner to improve electrostatic gate control, then gate control and short-channel control are improved, but the channel material becomes more susceptible to removal during chemical mechanical planarization
Solution Approach 1:
The patent transitions from a planar channel structure to a recessed channel structure by etching the channel region below the source and drain regions. This vertical dimensionality change allows the channel to be thinner for better electrostatic control while the source and drain regions remain elevated to protect the channel material during chemical mechanical planarization processing
Solution Approach 2:
The channel region is recessed and prepared in advance before the final planarization steps. This preliminary action creates a protected channel structure that is less susceptible to material removal during subsequent chemical mechanical planarization, allowing thin channel materials to be used without compromising manufacturing precision
2Reliability
If the channel region is recessed to improve short-channel control, then threshold voltage roll-off is reduced, but the device structure and fabrication process become more complex
Solution Approach 1:
The recessed channel structure is formed using self-aligned processes where the source and drain regions automatically define the channel boundaries. This self-service approach simplifies the fabrication process by eliminating the need for separate alignment steps, reducing the overall device complexity despite the enhanced three-dimensional structure
Solution Approach 2:
The patent combines multiple functions into the recessed channel structure: it provides short-channel control, defines the active channel region, and serves as a template for self-aligned source and drain formation. This merging of functions reduces the number of separate fabrication steps and lowers overall device complexity
Data Source
AI summary
A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.