Recessed Transverse Source Drain Contacts for FinFET Resistance Reduction
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Solution Overview
Problem
Conventional non-planar transistor structures, such as finFETs, face significant parasitic source/drain resistance due to longer, curved current paths, which hinders performance at highly scaled technology nodes.
Innovation Solution
The integration of recessed, transverse source and drain contacts with increased surface length, forming short, linear current paths from the channel to the contacts, and a second gate structure positioned at a specific distance from the first gate to enhance contact length and reduce parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional non-planar transistor structures (finFETs) are used, then device density and compactness are improved, but parasitic source/drain resistance increases due to longer, curved current paths
Solution Approach 1:
The patent introduces a second gate structure positioned at a specific distance from the first gate, creating a three-dimensional contact configuration. This dimensional addition allows contacts to extend beyond the conventional planar gate area, providing shorter and straighter current paths from the channel to the contacts, thereby reducing parasitic resistance while maintaining high device density
Solution Approach 2:
The patent pre-configures the contact geometry and positioning relative to the gate structures before final device operation. By establishing the contact surfaces at optimized positions and orientations in advance, the current paths are predetermined to be shorter and straighter, eliminating the need for post-fabrication adjustments and ensuring reduced parasitic resistance from the outset
2Reliability
If contact surface length is increased to reduce parasitic resistance, then source/drain resistance decreases, but device area increases
Solution Approach 1:
The patent applies different contact configurations to different regions of the device. The contacts are strategically positioned and dimensioned to provide increased surface length specifically where needed for current extraction, while other regions maintain compact dimensions. This localized optimization reduces parasitic resistance without proportionally increasing the overall device area
Data Source
AI summary
Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact.