Recessed UBM Pad Structure for Peel-Resistant Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in enhancing reliability and processability, particularly with the under bump metallization (UBM) pad, which affects the integration and performance of semiconductor chips.
Innovation Solution
The semiconductor package design includes a lower redistribution layer with insulating and conductive vias, a UBM pad positioned in a recess of a passivation layer, and a UBM protective layer covering the UBM pad, along with a method that involves depositing a UBM seed layer, forming a UBM pad, and etching to expose the UBM pad's bottom surface, ensuring a specific depth and preventing peeling-off phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the UBM pad is positioned flush with the passivation layer surface, then the manufacturing process is simpler, but peeling-off phenomena occur reducing reliability
Solution Approach 1:
The UBM pad structure is segmented into multiple depth levels relative to the passivation layer. The first UBM pad is positioned at a first depth while the second UBM pad is positioned at a second depth, creating a stepped configuration that prevents peeling-off while maintaining structural manageability through organized layering.
Solution Approach 2:
The solution transitions from a two-dimensional flush surface arrangement to a three-dimensional stepped structure by positioning UBM pads at different depths below the passivation layer surface. This vertical dimensionality change effectively distributes stress and prevents peeling-off phenomena.
2Adaptability or versatility
If more UBM pads are added for high integration, then connection density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The stepped UBM pad structure serves multiple functions simultaneously: it provides peeling-off resistance through depth positioning, enables high integration through increased connection density with first and second UBM pads, and maintains manufacturing feasibility through a systematic multi-layer approach that can be integrated with existing semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the semiconductor package by providing a stable UBM structure that prevents peeling-off and improves integration, leading to improved performance and manufacturing efficiency.
Implementation Method 1
a UBM protective layer disposed in the first recess of the lower passivation layer and covering a top surface and opposite side surfaces of the UBM pad
Implementation Method 2
etching a portion of the UBM seed layer, thereby forming a UBM seed pattern and exposing a portion of the PID release layer
Implementation Method 3
depositing an under bump metallization (UBM) seed layer on a photoimageable dielectric (PID) release layer, forming a UBM pad on the UBM seed layer
Data Source
AI summary
A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.


