Recessed Via Structure with Planarization Stop Layer
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Solution Overview
Problem
The formation of voids within via structures during the fabrication of semiconductor devices, particularly when using deposition methods like plasma vapor deposition or chemical vapor deposition for materials such as tantalum nitride or titanium nitride, poses a challenge in achieving reliable interconnects and memory stacks.
Innovation Solution
The solution involves forming a recessed via surface with a conductive planarization stop layer, which allows for the embedding of a conductor layer and fill material, resulting in a flat bottom electrode structure that reduces resistance and eliminates voids, thereby facilitating the formation of interconnects, metal stacks, or memory stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deposition methods like plasma vapor deposition or chemical vapor deposition are used for materials such as tantalum nitride or titanium nitride, then the via structure can be formed with appropriate barrier properties, but voids form within the via structure
Solution Approach 1:
The patent applies preliminary action by forming a recessed via surface before depositing the barrier layer and conductive metal. This pre-formed recessed surface allows subsequent materials to deposit uniformly without forming voids, as the depression compensates for material accumulation on vertical walls during deposition processes.
Solution Approach 2:
The patent changes the geometric parameter of the via structure by creating a recessed bottom surface instead of a flat or protruding one. This parameter change in the via profile enables uniform material deposition and eliminates void formation while maintaining the necessary barrier properties through conformal layer deposition.
2Ease of manufacture
If a flat via bottom surface is used, then subsequent processing is simplified, but voids form and resistance increases
Solution Approach 1:
The patent applies local quality by creating a recessed surface specifically at the via bottom where material deposition occurs, while the rest of the via structure maintains its original geometry. This localized geometric modification ensures uniform material distribution and low resistance without complicating the overall manufacturing process.
3Reliability
If conformal barrier layers are deposited in via openings, then the via structure gains proper barrier properties, but material accumulation on vertical walls creates non-coplanar surfaces
Solution Approach 1:
The patent forms the recessed via surface before depositing the conformal barrier layer. This preliminary action ensures that when the barrier material deposits conformally on the vertical walls, the recessed bottom provides additional space that compensates for the material accumulation, resulting in a coplanar top surface.
Solution Approach 2:
The recessed via surface acts as an intermediary geometric feature that mediates between the need for conformal barrier layer deposition and the requirement for coplanar surfaces. The recess absorbs the excess material volume from conformal deposition on vertical walls, allowing both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates void formation, leading to a flat bottom electrode structure with low resistance, enhancing the reliability and performance of subsequent interconnects, metal stacks, or memory stacks by ensuring a coplanar surface for further processing.
Implementation Method 1
depositing methods like plasma vapor deposition or chemical vapor deposition for materials such as tantalum nitride or titanium nitride
Implementation Method 2
A bulk conductor is deposited filling the via opening and forming an overburden thereon
Data Source
AI summary
A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure.