Recirculating TDC in Digital PLLs to Reduce Spurious Sidebands
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) in digital phase locked loops (DPLLs) suffer from buffer mismatches and unknown resolution, leading to spurious sidebands in the output signal spectrum, limiting their application in frequency generation where high spectral purity is required.
Innovation Solution
A recirculating TDC architecture with a period estimation loop is employed, which eliminates buffer mismatches by using rings with known delay times and inverters, and estimates the TDC resolution to provide accurate phase delay calculations, ensuring convergence of VCO and reference signals and reducing spurious sidebands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC architecture is used in a DPLL, then the phase measurement function is achieved, but buffer mismatches produce non-uniform quantization characteristics and periodic errors that appear as spurious sidebands in the output spectrum
Solution Approach 1:
The TDC is segmented into multiple identical buffer cells arranged in parallel paths. Each buffer cell processes a portion of the phase measurement, and the results are combined. This segmentation ensures that mismatches in one cell do not affect the entire system, and the periodic errors are distributed and reduced across multiple segments, thereby minimizing spurious sidebands while maintaining measurement precision.
Solution Approach 2:
The DPLL incorporates a feedback mechanism where the phase measurement from the TDC is used to adjust the VCO frequency, and the process is repeated. This feedback loop allows the system to continuously correct for any residual errors from buffer mismatches, improving phase measurement accuracy over time and reducing the impact of spurious sidebands through iterative refinement.
2Measurement precision
If a conventional TDC architecture is used, then phase difference measurement is provided, but the resolution is not known precisely due to process, voltage, and temperature dependence
Solution Approach 1:
The TDC design incorporates buffer cells with carefully controlled and matched parameters that are designed to be insensitive to process, voltage, and temperature variations. By selecting operating points and designing buffer characteristics that minimize PVT sensitivity, the resolution becomes more predictable and reliable across different operating conditions, enabling accurate phase difference measurement without requiring precise knowledge of the absolute resolution value.
3Ease of operation
If the TDC resolution is not precisely known, then the phase wrapping effect periodically resets the incorrect phase difference, but this creates spurious sidebands that require low bandwidth DPLL filtering
Solution Approach 1:
By segmenting the phase measurement into multiple buffer cell outputs, the effective phase wrapping period is extended. Instead of a single buffer determining the wrapping point, multiple buffers provide a more granular and extended measurement range, reducing the frequency and impact of phase wrapping events that would otherwise create spurious sidebands.
Solution Approach 2:
The system uses periodic phase measurements from the TDC within the DPLL feedback loop to continuously track and correct phase differences. By maintaining continuous periodic measurement and adjustment, the system can handle phase wrapping events smoothly through the feedback mechanism, preventing the creation of spurious sidebands even when absolute resolution is not precisely known.
Data Source
AI summary
An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.