Reconfigurable SAR ADC With Noise Shaping for Adaptive Audio Power
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) in computing devices either consume excessive power for high-quality audio or conserve power at the cost of lower audio quality, failing to adapt to varying user needs and draining batteries quickly.
Innovation Solution
A reconfigurable ADC that includes a successive-approximation-register (SAR) ADC, noise-canceling circuit, and noise-shaping circuit, enabling dynamic operation modes to support varying audio quality, bandwidths, and sampling rates while conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sigma-delta ADC is used to support high-quality audio, then audio quality is improved, but power consumption increases
Solution Approach 1:
The patent implements a reconfigurable ADC that can dynamically switch between different conversion modes (sigma-delta and SAR) and adjust resolution settings based on real-time audio quality requirements. This dynamic adaptation allows the system to use high-resolution sigma-delta mode only when high-quality audio is needed, while using lower-power SAR mode for typical applications, thus resolving the contradiction between audio quality and power consumption
Solution Approach 2:
The patent changes the operational parameters of the ADC by implementing multiple resolution settings (e.g., 18-bit, 16-bit, 14-bit, 12-bit ENOB) and allowing dynamic adjustment of sampling rates and bandwidth. By changing these parameters according to application needs, the system achieves high audio quality when required while consuming less power during normal operation, effectively resolving the contradiction
2Use of energy by moving object
If a SAR ADC is used to conserve power, then power consumption is reduced, but audio quality deteriorates
Solution Approach 1:
The patent makes the ADC reconfigurable between SAR and sigma-delta modes, allowing the system to dynamically select the appropriate conversion mode based on audio quality requirements. When high audio quality is needed, the system switches to sigma-delta mode despite higher power consumption, while using SAR mode for power-critical applications, thus resolving the contradiction
Solution Approach 2:
The patent creates a universal ADC architecture that can perform both SAR and sigma-delta conversion functions within a single device. This multi-functionality allows the system to adapt to different audio quality requirements without needing separate ADCs, enabling power savings when high quality is not needed while maintaining the capability for high-quality audio when required
3Measurement precision
If fixed high-resolution ADC is used to support high-quality audio, then audio quality is maintained, but battery life decreases
Solution Approach 1:
The patent implements dynamic resolution adjustment where the ADC can switch between different ENOB settings (18-bit, 16-bit, 14-bit, 12-bit) based on application requirements. By using lower resolution settings for typical applications and only engaging high-resolution mode when absolutely necessary, the system maintains audio quality when needed while significantly extending battery life during normal operation
Solution Approach 2:
The patent changes the resolution parameter dynamically based on application needs rather than maintaining a fixed high-resolution setting. The system can adjust ENOB, sampling rate, and bandwidth parameters to match the actual audio quality requirements, thereby preserving battery life while maintaining the capability for high-quality audio when required
Data Source
AI summary
This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.