Reconfigurable Address Generation Circuit for Image Processing
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Solution Overview
Problem
Existing reconfigurable integrated circuits face limitations in processing image data due to the need for multiple processor elements to generate read addresses for pixels at the edges of an image frame, which increases complexity and reduces efficiency.
Innovation Solution
A reconfigurable address generation circuit that uses X and Y counters, clip processing circuits, and an address calculation circuit to dynamically generate read addresses based on configuration data, including edge information, allowing for efficient address generation for image data across multiple rows and columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor elements are used to handle edge pixels during image processing, then processing capability is improved, but device complexity and resource usage increase
Solution Approach 1:
The address generation circuit is designed to perform multiple functions: it generates addresses for normal pixels, detects edge pixels, and generates addresses for surrounding pixels of edge pixels all within a single circuit. This multi-functional design eliminates the need for separate processor elements to handle different pixel types, thereby maintaining high processing capability while reducing device complexity.
Solution Approach 2:
The address generation circuit includes self-detection capability for edge pixels through the edge determination circuit. The circuit automatically identifies when it is generating addresses for edge pixels and autonomously adjusts its behavior to generate appropriate surrounding pixel addresses, eliminating the need for external control or additional processing elements.
2Productivity
If multiple processor elements are used to handle edge pixels during image processing, then processing capability is improved, but resource usage increases
Solution Approach 1:
The address generation circuit is designed to perform multiple functions: it generates addresses for normal pixels, detects edge pixels, and generates addresses for surrounding pixels of edge pixels all within a single circuit. This multi-functional design eliminates the need for separate processor elements to handle different pixel types, thereby maintaining high processing capability while reducing device complexity.
Solution Approach 2:
The invention combines the address generation function, edge detection function, and surrounding pixel address generation function into a single integrated circuit. By merging these previously separate functions into one circuit, the total resource usage is reduced while maintaining the processing capability to handle all pixel types efficiently.
3Adaptability or versatility
If a reconfigurable address generation circuit is used, then adaptability is improved, but device complexity increases
Solution Approach 1:
The address generation circuit employs dynamic reconfiguration through configuration data that can be loaded at runtime. The circuit structure changes based on the processing requirements, allowing it to adapt to different image processing tasks while maintaining a relatively simple base structure. This dynamic adaptability is achieved through controlled reconfiguration rather than complex static design.
Solution Approach 2:
The reconfigurability of the address generation circuit is achieved by changing parameters such as pixel unit size, block size, and processing mode through configuration data. Rather than requiring complex structural changes, the circuit adapts by modifying its operational parameters, which simplifies the overall device design while maintaining high adaptability to different image processing requirements.
Data Source
AI summary
A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.