Reconfigurable Multilayer AI Network ASIC for Flexible Model Updates
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Solution Overview
Problem
Existing AI network implementations on ASICs for image processing lack flexibility to accommodate updates or improvements in AI models without requiring significant redesign or increased hardware complexity and cost.
Innovation Solution
A reconfigurable multilayer AI network on an ASIC, where each layer includes a plurality of multiplier-accumulator (MAC) units that can be partitioned into blocks to operate independently or in combinations, enabling the implementation of different AI models by reconfiguring the input depth size, output feature map size, or adding virtual layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AI networks are optimized based on a specific training model to increase speed and efficiency of inferencing operations, then the inferencing performance is improved, but the hardware becomes inefficient when the training model is updated or improved
Solution Approach 1:
The AI network is divided into multiple independently reconfigurable blocks of MAC units within each layer. Each block can be independently configured or combined with other blocks to support different AI model architectures. This segmentation allows the hardware to be reconfigured for different models without redesigning the entire chip, resolving the contradiction between optimization for a specific model and flexibility for model updates.
Solution Approach 2:
The patent implements dynamic reconfigurability where the arrangement and connectivity of MAC unit blocks can be changed based on the required AI model. The system transitions from a static hardware design optimized for one model to a dynamic architecture that can adapt its configuration. This enables the same hardware to maintain high inferencing performance across different model versions without physical redesign.
2Device complexity
If the AI network uses a fixed architecture optimized for a specific model, then the hardware complexity is reduced, but the adaptability to implement different AI models is limited
Solution Approach 1:
The patent creates a universal AI network architecture where the same set of reconfigurable MAC unit blocks can implement multiple different AI models by changing their arrangement and connectivity. This multi-functional design allows a single hardware platform to support various image processing tasks and model architectures, eliminating the need for separate dedicated hardware for each model while maintaining relatively simple block-level complexity.
3Adaptability or versatility
If the AI network is designed with reconfigurable blocks to support different AI models, then the adaptability is improved, but the hardware complexity increases
Solution Approach 1:
By segmenting the network into standardized MAC unit blocks, the patent manages complexity at the block level rather than requiring complex reconfiguration of the entire architecture. Each block is a simple, standardized unit that can be independently configured, making the overall system more manageable and less complex despite the reconfigurability.
Solution Approach 2:
The patent employs a hierarchical structure where smaller MAC unit blocks are nested within larger blocks, which in turn are nested within complete layers. This nesting allows for modular reconfiguration where blocks can be combined in different ways to form different network architectures. The nested structure provides a systematic approach to reconfiguration that reduces the effective complexity by breaking down the reconfiguration problem into smaller, manageable steps.
Data Source
AI summary
This disclosure provides methods, devices, and systems for an artificial intelligence (AI) network. The present implementations more specifically relate to an AI network on an application specific integrated circuit (ASIC) operable as a reconfigurable multilayer image processor capable of implementing different AI models. In some aspects, each layer in the multilayer AI network includes a plurality of multiplier-accumulator (MAC) units, and at least one layer is partitioned into a plurality of blocks of MAC units that are reconfigurable to operate independently or to operate in one or more combinations of blocks of MAC units. The arrangement of the plurality of blocks of MAC units in the at least one layer enables implementation of one or more virtual layers, reconfiguration of the input depth size, reconfiguration of the output feature map size, or a combination thereof, which may be used to executes a desired AI model for image processing.