Reconfigurable Arithmetic Circuit for Low-Latency Parallel Compute
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Solution Overview
Problem
Existing computing systems face limitations in computation speed, energy efficiency, and scalability for mathematically intensive applications such as artificial intelligence, neural networks, and blockchain, with inadequate performance and excessive energy consumption.
Innovation Solution
A reconfigurable processor architecture with scalable computational cores, capable of low latency and energy-efficient processing, featuring a configurable multiplier, input reordering queues, and an accumulator circuit, allowing for real-time data processing and massively parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing computing systems are used for mathematically intensive applications, then computation processing is performed, but computation speed is insufficient and energy consumption is excessive
Solution Approach 1:
The computing system is divided into multiple computational cores that can operate in parallel. Each core is a self-contained unit capable of independent computation, allowing the system to process multiple mathematical operations simultaneously, thereby increasing overall computation speed while distributing energy consumption across multiple units.
Solution Approach 2:
The computational cores are designed to be reconfigurable, allowing their internal structure and operations to be dynamically adjusted based on the specific computational task. This enables optimization of both speed and energy efficiency by adapting the computing architecture to match the requirements of different mathematically intensive applications such as neural networks, blockchain, and encryption.
2Productivity
If computational cores are increased to improve processing capability, then computation performance improves, but device complexity increases
Solution Approach 1:
Each computational core is designed as a universal unit capable of performing multiple types of mathematical operations including multiplication, addition, and various logical functions. The cores can be configured to handle different application requirements through reconfiguration of their internal logic, allowing a single standardized design to serve multiple purposes and reducing overall system complexity.
Solution Approach 2:
The computational cores are organized in a hierarchical structure where multiple cores can be nested within larger processing units or arrays. This nested arrangement allows for scalable deployment where simple configurations can be easily expanded to more complex ones by adding or removing core units, managing complexity through modular organization.
3Adaptability or versatility
If reconfigurability is added to optimize hardware for selected applications, then adaptability improves, but device complexity increases
Solution Approach 1:
The computational cores utilize configurable parameters such as operand sizes (e.g., 8x8, 16x16, 32x32 multipliers), operational modes (fixed-point, floating-point), and data path configurations that can be adjusted through control signals. These parameter changes allow the same hardware structure to adapt to different application requirements without requiring physical reconfiguration, maintaining simplicity while achieving versatility.
Data Source
AI summary
A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.